LVS DEBUG SOLUTIONS LLC

Arya Raychaudhuri,  Ph.D.

[Founder, Owner, Sole Member at LVS DEBUG SOLUTIONS LLC, a California (CA)  Limited Liability Company (LLC)]

[Basic Points: Ph.D. in MOSFET modeling, Canadian Commonwealth Scholar, 1991, 20+ years on Calibre PV platform, shell/perl/tcl/svrf based novel application softwares, *Active* proponent of running Moore's Law in the transverse direction through circuit innovations, male/female IP based designs, piston-pawl drive, direct decimal arithmetic circuits, electro-mechanics controls, amphibian transportation, analog MOS ckts with short channel fets, new multi-AC generator,  green energy components, spring tooth based machines/engines, etc.]

(nickname: Mithu)

Health status - Post-liver transplant ultrasounds at 4, 6 months normal/stable. Recently averted a dangerous drug overdose, phew! The psycho-somatic fatwa like disturbances (the "genocidal innuendo") continues ...

E_mail: arya@lvs-debug-solutions.com

gmail: arya.raychaudhuri@gmail.com

Phone: 408-480-1936 (cell)

980 Kiely Blvd, Unit 308

Santa Clara, CA 95051 USA

(homeowner)

 

Expertise/Work Interest:

FullChip Tapeout Expertise in Calibre Physical Design Verification (~25 full chips LVS, DRC debugged and taped out so far) , ruledecks development using Calibre SVRF (75 such), complex LVS/DRC debug on IcStation, Virtuoso, CalibreDesignRev platforms. Special purpose application code development using TVF/SVRF (compile-time/run-time TVF), CalibreDRV-TCL and Shell/Perl for automated physical design generation, modification and translation from one tech node to another, for Shorts Isolation, Yield-sensitive structures mapping, Stress Vias and Via opportunities identification and addition, fullchip Power Planes generation, metallization/actives changes for DFM and chip integration (putting sub-blocks together, editing sub-blocks). Layout extraction with Calibre XRC. Addressing run-time and hierarchy issues.  Atoptech-based  block level PD work, Primetime reports parsing for setup/hold time fixing. Perl recursives  for SPICE Analysis. Perl/Shell based modification of verilog/cdl netlists (for v2lvs) to help multiple voltage domains LVS, Perl based PDV flow development. Hercules LVS.

Pervasive digital, analog, electro-mechanics, and  mechanical IPs, also Electricity generation and propagation concepts [With deep earlier experience in Device Physics/Modeling, Process/Device Simulation, and Spice Modeling, Previous strong background in computer controlled measurements out of wafer-probers (experience certificates)]

WORK STATUS: Naturalized US citizen, OCI India

Most recent international travel: India, Germany, Dec'19-Jan'20

[see picture in the >>breakroom page]

Last voted on: March 3, 2024  (mail voting)

Summoned for federal jury duty: excused

Summoned for state jury duty: participated, excused

Apr 2024 FICO score (TransUnion) : 840

Federal & State Taxes Filed : 4/14/2024

Hobbies: Cardio workout 24 hour fitness, motorcycling, tetris (for brain frequency), miniclip computer games, walking, badminton

Special Interest: Creative Writing on socio-cultural issues on soc.culture.bengali (a google news group) - evolving a new state model called Ekballpore, a literary device. Newsgroups blogger for the last 25+ years. Proponent for non-causal developments that involve sharp departure from past practices, or let the effects dictate the causes. Also wrote on information racism and medical racism issues - since they can delay/stop the appreciation/acknowledgement of engineering and other creative works, help decrease one's social confidence.

Languages: English, Bengali (mother tongue), Hindi

EXPERIENCE:

Current Interests:

Calibre LVS Debug Work/Applications, and/or

Creating A Center for Innovaions and Early Development around my IPs, Selling Concepts, Small Business getting acquired

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4/2022 -  12/2023; 03/2024 - continuing  : LVS DEBUG SOLUTIONS LLC  project with Raxium (Google), Fremont, CA 

1st Milestone of the mega-pixels integration/verification achieved - high points included 1. fixing 1.87M+ wide metal DRC errors with a calibre svrf script, 2. complete LVS with 1.6M+ output ports, 3. Fixing density issues of LED Vias with Calibre

2nd Milestone in 22nm tech node  Mega-Pixels power plane/mesh creation with IR drops surface optimization. Power/Ground hookups to lower sub-cells from topMesh (power routing) with Calibre. Physical Verification. Project taped out in early December, 2023. Chip works!

6/2022 -  9/2022:   : LVS DEBUG SOLUTIONS LLC  project with Samsung, San Jose, CA   (partial engagement)

LVS Debug done successfully for  14nm and 8nm finfet-based Full digital merges (top blocks+pnr's) for chips geared towards cellphone applications, SVRF/tcl scripting for debug/flow ....

9/2020 - continuing: Tech content development for  LVS DEBUG SOLUTIONS LLC

Item#487 onwards in

code_snippets4

code_snippets5

(Unpaid activity for self-owned small biz, creative investment into the small biz)

2/2019 -  8/2020   : LVS DEBUG SOLUTIONS LLC  project

with Jasper Display Corporation, Santa Clara, CA

Calibre Physical verification for two full tapeouts, one metals only tapeout; extensive IRdrop analysis using Calibre XRC and finesim circuit simulator, expanding on the basic principle earlier discussed in Item#87 - generating IRdrop surface plots for mega-pixel pixarrays. Massive Calibre based DRC and powerRails IRdrops  fixing with flow. Perl flow to take Calibre generated nets data to DEF format. Circuit concept for processing serial video data to PWM pixel data; new shell algorithm to extract design tree from spice netlist, Calibre pathchk constructs to detect inter-voltage domains paths, etc.

11/2018 -  1/2019: LVS DEBUG SOLUTIONS LLC project

with Avago/Broadcom, San Jose, CA

Chip surgery and physical verification with Calibre

8/2016 - continuing: Tech content development for  LVS DEBUG SOLUTIONS LLC, started in July 2012

code_snippets2 

code_snippets3

http://lvs-debug-solutions.com/code_snippets4

code_snippets5

[The >> code snippets page was already developed with work done alongside projects, srarted in July 2012]

Item#219 onwards ... speed of innovation and forward looking developments ... Over 260 new snippets so far (revenue /jobs generating creative ideas involving multiple *mechanisms* and *emulators* catering to various engg sectors)

(Unpaid activity for self-owned small biz, investment into the small biz)

3/2016 - 7/2016 : LVS DEBUG SOLUTIONS LLC project

Finished a 40nm multi-chip module PV --> Tapeout  for Avago/Broadcom, San Jose, CA

• Automated sub-block swap and PV flow, batch mode AP-Calibre DRC correction, sealRings/interconnectors transformation with Calibre

• Perl hash based DRC db segmentation for textual waiver XOR - relevant for edge errors in drc db

• Improved batch mode AP, Calibre based antenna nets queryer flow

• Calibre based fanout analysis - finding top 10 high fanout net names [Note: when a layout is LVS CORRECT, many logical issues translate to the physical design, so one can analyze them even with something like Calibre's search engine functions]

***

12/2015 - 2/2016 : LVS DEBUG SOLUTIONS LLC project

Helped Eximius Design LLC, San Jose, CA  on a 28nm ICV Tapeout with Calibre analytics ...

ICV PV flows, FullChip ICV debug to LVS PASS, Calibre shorts finder coding in Calibre to overcome a slip in connectivity with the LVS deck. and isolation cells analysis with Calibre. [isolation cells allow passing signals from power shutdown domains to always on domains w/o exposing inputs to undefined states], Via antenna net queryer flow (perl/svrf/shell) around a third party def file parser (perl)

***

5/2015 - 11/2015: CAD Engg contractor at Intel, Santa Clara, CA (through Aditi Staffing)

• Looking at Intel ICF's  customer testcases regression for physical verification - comparing Calibre versus ICV verus PVS platforms, using  14nm designs

• CalibreDRV macros, net tracing svrf for better DRC/LVS debug, core CalibreTVF procedure for binned DRCs, Perl script to logically filter out #IFDEF, #IFNDEF, #ENDIF etc from SVRF decks

• Degugging runtime, methodology issues - rootcaused

11/2011-present Proprietor, LVS DEBUG SOLUTIONS, LVS DEBUG SOLUTIONS LLC (Sunnivale, CA, Santa Clara, CA)

Projects Done so far:

• First multi-chip module tapeout LVS with Calibre, metals respins for a single chip, hspice based dynamic/static leakage power calculation for a digital sub-block, via densitity adjustment with calibre. A multi-chip is several fullchips connected together in a complex conundrum. - for PLX Tech, Sunnyvale, CA

Second multi-chip module physical verification work - tapeout in June 2014 - for PLX Tech, Sunnyvale, CA

• Developed the code snippets page indicating new LVS ideas and fundamentally interesting new shell/perl/svrf/tvf/tcl/spice codelets, digital design IPs, new Gear systems [Unpaid activity for self-owned small biz] - over 200 snippets presented as of March 2015, and 90 snippets added since July 2014.

* eSilicon (Sunnyvale, San Jose, CA) projects - first tapeout (40nm) Jan 2013, second tapeout (28nm) Feb 2013, third tapeout (40nm) early April 2013, fourth (40nm) in May 2013, crucial assitance to a fifth fullchip LVS debug (40nm) in Sept 2013

12/2007- 10/2011 Fulltime - part time - Fulltime again: Fastrack Design,, San Jose, CA, Senior Staff Design Engineer (Calibre PDV) - PDV Manager

• Atoptech-based  block level PD work, Primetime reports parsing for setup/hold time fixing.  Perl recursives for spice analysis – tree extraction with net trace.

• Worked on FullChip Tapeout for various customers doing designs in TSMC90, Chartered90, TSMC65, TSMC130, TSMC180, TSMC250, Fujitsu65, Fujitsu90, TSMC40, Toshiba40nm processes. Mainly in Calibre, one tapeout in Hercules.

• Electronic Design paper on using Calibre for Layout Generation and Modification

http://www.electronicdesign.com/embedded/correct-construction-layout-generation-and-modification

Full manuscript on 

calibre_papers

Electronic Design Paper on DRC/ERC data splitting algorithm http://electronicdesign.com/fpgas/programmed-splitting-full-chip-calibre-drcerc-errors-sub-block-space

Full manuscript on

calibre_papers

Siemens EDA Archives Paper on Perl-Calibre based Junction Vias Deficiency Checker/Adder  [moved from eetimes]

https://www.techonline.com/tech-papers/chip-ir-drop-reduction-through-automated-via-checking-and-addition/

Full manuscript on 

calibre_papers

• Developed specialized SVRF code, Perl/Shell/tcl scripts for problem solving. DFM work with Cadence LPA, CCP. Spice simulations.

12/2010 – 12/2011 (moonlighting consultant): Jasper Display, Santa Clara, CA

• CalibreDRV-TCL, Shell, Perl based GDS design conversion from TSMC to Fujitsu design rules, various shell/perl flows for Calibre

5/2009- 6/2009 (full-time contract): Uniquify Consultant, Santa Clara, CA

• Calibre LVS for tapeout

1/2007 - 11/2007: Ikanos Communications, Fremont, CA Contractor/Full-time Engineer

• Helping resolve tapeout PDV issues in Calibre DRC/LVS/ERC

6/2004 - 3/2006: Advanced Micro Devices, Sunnyvale, CA MTStaff Design Engineer

• Calibre SVRF, Calibre-DRV TCL, Perl-based Complex Layout Generation (such as fullchip powerplanes), layout Modification
• Development of Calibre techfiles for complex fullchip layout debugs - such as pinpointed signal to non-signals, power-ground shorts isolation (using DRC method), metals pitch profiling and mapping to predict possible metal-bridging locations on chip (using LVS method).
• Development of Perl-Calibre-TCL solutions for fullchip DRC debug - filtering DRC errors for sub-blocks interfaces, locating/modifying cells instances with specific properties, fullchip DRC  runtimes profiler to isolate slow checks

6/2002 - 10/2003: Sun Microsystems Sunnyvale/CA Physical Design Verification Lead

• Leading physical design verification efforts through incorporating new flows and procedures for complex verification tasks. Such as multiple supply voltages design rules checking through domain separation. Efficient and effective redundant (metal stress related) Vias checking. Via opportunities/ERC techfile. Enhancement of the display of metal density results. Calibre-based extraction of the flipchip pads maps. DRC regression test cases generation and automated running. DRC/LVS debug of fullchip and sub-blocks using Vituoso and Calibre.

6/1997 - 6/2002: Rockwell/Conexant, Newport Beach, CA Manager, Layout and Technology Analysis

• Main Developer of Physical Verification and Extraction decks for post-layout verification and extraction, based on Mentor’s Calibre/xCalibre SVRF.  Many companies in Irvine area use those decks.
• Supported designs in CMOS, BiCMOS, Bipolar, Analog, Mixed-Signal, Silicon-Germanium, and GaAs technologies. Design rules review.
• Managed a small group of 4 engineers working in physical verification/extraction areas.

8/1996 - 5/1997: PMC Sierra Inc. Vancouver, B.C. Layout Verification Engineer

• Developing layout verification code for CMOS designs on Mentor Platform, after training with Mentor Graphics.

1/1996 - 7/1996: Glenayre R&D Inc. Vancouver, B.C. Signal Processing Engineer

• Modeling of r.f. power amplifiers from system perspective, using Matlab.

9/1991 - 12/1995: Simon Fraser University Burnaby, B.C. Graduate Research Assistant

• Developed a virtual factory-type simulation environment using SUPREM4 and MEDICI on the UNIX using SHELL and C programs.
• Analysed the early mode of the hot carrier degradation using floating gate, charge pumping, and transconductance techniques, as well as simulation.
• Designed a new static memory scheme using resonant tunneling diodes. Worked with HP-VEE and AURORA.

5/1993 - 9/1994: Northern Telecom Ltd. Nepean, Ontario Co-op Research Student

• Investigated hot-carrier reliability, and impact ionization-induced substrate and gate currents for sub-micron NMOS devices using extensive measurements and simulation. Coauthored two company technical reports in the TCAD area.

10/1987 - 7/1991: Indian Institute of Technology (IIT) Kanpur, UP Senior Research Engineer

• Analyzed the impact of ion-beam damage on thin oxide MOS structures using admittance spectroscopy and ellipsometry. Modelled the electrical features of such damage. Multiple research publications.
• Developed software for data acquisition and data analysis using HP semiconductor test system and other HP and Keithley equipments. The software was written in HP-BASIC.

10/1983 - 10/1987: Semiconductor Complex Ltd. Mohali, Punjab Member, Technology Development Team

• SUPREM process simulation. Designed and developed a process evaluation test chip for a 3-micron CMOS process developed in-house. Formulated complete topological design rules for all mask levels of 3-micron CMOS layouts corresponding to the above-mentioned process.
• Developed improved techniques for short channel MOSFET parameter extraction and modeling (published SCL’s first IEEE Transactions paper http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=2436&contentType=Journals+%26+Magazines -early thoughts on surface potential based modeling).
• Designed and developed an electrostatic-discharge (ESD) protection networks test chip for comparison of various options.

EDUCATION

• 6/1996: Simon Fraser University Canada-B.C.-Burnaby

Ph.D.  : (course work + comprehensives + thesis) Thesis title: Modeling and simulation of saturating hot electron degradation in LDD NMOSFETs - from early mode to late mode. [170+ citations for the constituent papers, thesis nominated for Douglas Colton medal, a Northern Telecom supported project,  strong post-PhD creative contribution in electronics and electro-mechanics]

1996 Oct Convocation listing in: atom.archives.sfu.ca

PhD thesis:

https://summit.sfu.ca/_flysystem/fedora/sfu_migrate/6998/b18000745.pdf

[download pdf in a separate window, read in a pdf reader]

CommonWealth scholarship interview succes.

• 7/1983: Jadavpur University (Electronics & Telecom. Dept.) India- West Bengal-Calcutta

M.S.  : 1983, Specialization in electronic devices, thesis on switching speed of a novel MOSFET inverter.  Coursework Percentage of Marks: 72.7.

B.S.  : 1981, Electronics & Telecommunication Eng. GPA 3.64

WB Joint Entrance test based entry, rank 21

B.S.  : attended in 1976 - Aeronautical Engg, IIT Kharagpur, moved to JU after one and half months. Got introduced to the law of causality for the first time in a physics class

IIT Joint Entrance test based entry, all india merit list rank 1198

• 3/1976: WestBengal Board of Secondary Education

H.S.  : after 10 years (grade II through grade XI, grade I homeschooled) of schooling at Mitra Institution (Bhawanipur),   Calcutta - final subjects: Bengali, English, Physics, Chemistry, Math, Mechanics:  First Division

Admission test based entry.

ADDITIONAL INFORMATION: Academic Honors

• Awarded National Scholarship, India in 1976.
• Canadian Commonwealth Scholarship, 1991.
• Graduate Fellowship, 1992, Simon Fraser U.
• President’s Research Stipend, 1993, Simon Fraser U.
• Dean’s Scholarship, 1994, Simon Fraser U.
• Hector J. MacLeod Award, 1995,IEEE, Vancouver Section.
• publications have been well cited (>125)in international journals .
• I have been asked to review publications for IEEE (EDS).

Key(Kn) Publications (Look in scholar.google.com for more)

[K0] A. Raychaudhuri, Items and Snippets for LVS DEBUG SOLUTIONS LLC, 2012-2020

code_snippets

code_snippets2

code_snippets3

code_snippets4

[K1] A. Raychaudhuri, W.S. Kwan, M.J. Deen, and M.I.H. King, Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs, IEEE Trans. on Electron Devices, ED-43, 1114-1122 (1996).

https://ieeexplore.ieee.org/abstract/document/502423

[K2] A. Raychaudhuri, Z. X. Yan, M. J. Deen, and A. C. Seabaugh, Hysteresis in resonant-tunneling-diode-based multiple-peak driver  device for multivalued SRAM cells: analysis, simulation, and experimental results, Canadian Journal of Physics, 70, 993-1000 (1992).

http://www.nrcresearchpress.com/doi/abs/10.1139/p92-159

[K3] A. Raychaudhuri and M.J. Deen, New static storage scheme for analogue signals using four-state resonant-tunneling devices, Electronics Letters, 29, 1435--1437 (1993).

https://digital-library.theiet.org/content/journals/10.1049/el_19930961

[K4] A. Raychaudhuri, M.J. Deen, M.I.H. King, and J.Kolk, Finding the Asymmetric Parasitic Source and Drain Resistances from the A.C. Conductances of a Single MOS Transistor, Solid-State Electronics, 39, 909-913 (1996).

http://www.sciencedirect.com/science/article/pii/0038110195002693

[K5] A. Raychaudhuri, S. Chatterjee, S. Ashok, and S. Kar, Ion-dosage- dependent room-temperature hysteresis in MOS structures with thin oxides, IEEE Trans. on Electron Devices, ED-38, 316-322 (1991).

https://ieeexplore.ieee.org/abstract/document/69912

[K6] Arya Raychaudhuri, New product idea: Adio-visual newspapers, published on soc.culture.bengali, March 22-26, 2009

https://groups.google.com/g/soc.culture.bengali/c/NTufzeHines

 Looking for partial engagement  - project/job related to:

Calibre LVS Debug Work/Applications, and/or Creating A Center for Innovaions and Early Development around my IPs

--------------------------------

Arya Raychaudhuri

Highest Work Achievement to date: 500+ code snippets for LVS DEBUG SOLUTIONS LLC since  July 2012

[Most codes and circuit snippets concept proven (tested/simulated)]

Turning LVS DEBUG SOLUTIONS LLC into an engineering concepts company;  concepts that can benefit the entire world - asia, europe, africa, latin america,  and north america. Seeking reciprocal tech enthusiasm, buyers

Broad Categories of Conepts created

[look in https://www.lvs-debug-solutions.com, look up the code snippets* pages]

[For example, over one billion people of the world don't have access to electricity, and here you have the multi-AC ....Water Wheel Farm for generating electricity, other 'green' energy schemes]

[Boatmen around the world on row-boats will no longer need operate the heavy oars - here you have the pawl rack pinion (PRP) drive ...]

[Spring-toothed rack and  regular pinion (PRP), regular rack and spring-toothed pinion (PP) drives. Also, electro-magnetic (EM) tooth collapse versions of PRP, PP drives]

[Automobile transmission design based on EM spring-toothed pinion (the pawl gear) and fixed toothed pinion]

[Reciprocatory to circular motion, relative speed meshing properties of the PRP and PP drives exercised in manually driven vehicles and boats, non-motor EM engine, more efficient windmill power transfer]

[Circular Aerofoil and Hydrofoil considerations, simpler Lift, Drag measurement scheme]

[Rickshaw engine based on hand-operated road friction]

[Taking advantage of the Early effect in short MOSFETs to build linear amplifiers, non-Early effect in long MOSFETs to build constant current chargers ...]

[Circuit minimization of shift stages and flipflops using competitive conduction modes in component MOSFETs, and FETs bundling]

[*Direct* decimal integer arithmetic circuits - Full adder, Full subtractor, Full comparer]

[Bash shell script based dynamic emulation of clocked digital circuits]

[Recursive/non_recursive algorithms with shell, perl to extract Trees/flatten circuits/find graph paths; Parsers; process forking to model parallel circuit operations]

[Design methodology using pulse generating (male) and pulse counting (female) bricks - PGEN  and VMON; diverse applications]

[clk-to-q reduced (taking advantage of the inevitable gate delays) bi-directional shift registers in chains and mazes; applications]

[Pulse edge driven logic operations coupled with clock splitting with the ANDs pipe for fast sub-clock period switching]

[What is Transverse Moore's Law (TML)? Chip size reduction by circuit minimization/reduction for the same function. Speed increase through smaller circuits, and through ANDs pipe driven shifts]

[Electro-mechanics control circuit for tracking variable reference levels, e.g., the Jetty Height Control (JHC) circuit, in connection with the amphibian transportation model]

===================

Serious collaborators, please feel free to check and verify  the originals of the credentials presented below

--------------------------------

Phd Degree/thesis approval

thesis nominated for Douglas Colton medal:



PhD Supervisor's Comments:

**170+ citations of PhD papers (as per scholar.google.com, keyword: "Raychaudhuri + Deen"), 

Northern Telecom (Nortel) work certificate

SFU congratulates for grad work as  CommonWealth Scholar

---------------------------------

Interesting work done at IIT Kanpur (below)

First and very vital exposure to LSI/VLSI at SCL (Mohali, Punjab) - see below

 ===============

First introduction to the popular book, Device Electronics for Integrated Circuits, by Muller and Kamins, at the M.E. level

M.E. Degree certificate

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Learned to do FORTRAN  programming on a Burroughs 6700 mainframe computer, using punched cards, dozens of courses and labs taken at the B.E. level



B.E. Degree certificate

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Most favorite subject at higher secondary level - Mechanics (statics and dynamics)

Higher Secondary certificate

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ACM member certificate...