LVS DEBUG SOLUTIONS LLC

Item#307> Parallel implementation of a 3-digit Full Adder using 3 half Adders (Item#s 298, 301, 306)

Only one of the multiple half Adders' ANDs pipes need to be edited for post-parallel-halfAdd  carry add.  Please note how the post-parallel-halfAdd result 1894 turns into carry-added 1904. Only the bit movements are indicated by the green arrows

[June 15, 2017, Arya Raychaudhuri, Santa Clara, California]

Obvoulsy, this full Adder works in half Adder time plus another two edges for the carry adds - much faster than the sequential mode (Item#304). From this example, one can estimate that a 10-digit direct decimal adder will  work in one and half times the time taken by a half Adder, when 10 half Adders run in parallel as in the scheme shown above.

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Item#306> Generation of the edges and dips mentioned in Item#305

Looking at the ANDs pipe only and its edits, and not the other logic and registers shown in Item#s 298,301 

[June 15, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#305> Some useful pulses/edges used in the implementation of the full Adder of Item#304 explained

[June 14, 2017, Arya Raychaudhuri, Santa Clara, California]

The edge A which is the clk rising edge is used to read in the spice input data into the left and right add data registers. The edge B which is delayed edge A makes the carry add to the left column when previous carry is 1. The edge C which is the delayed edge B, initializes the sum register's 0 bit to 1, and the carry bit to 0 - it also starts a latch that initiates the half adder action. 

On the cycle ending side, the exx  dip D is used to clean up the trailing ends of the moving pulse inside the ANDs pipe. It also helps generate the edges E, F at its rising and falling. E is used to reset the left and right add registers, F is used to reset the sum register but not the carry bit. E, F also define a latch opening to output the sum results of the preceding add - see V(fa*) in Item#304.

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Item#304> A sequential mode 3-digit Full Adder based on the half Adder of Item#298 simulated

Two cases are shown below - spice data input, followed by the simulation results. In the simulation results, the left most pane shows the 13ns clock used, the next pane shows the transferred  contents of the left column addendum, with carry related shifts if/when it occurs, the third pane shows the transferred contents of the right column addendum, the next pane shows the FullAdder sum digits as output after each digit add, the fifth column shows the carry bit movements, the sixth shows the result register shifts. Please, note that the final result includes the Sum digits preceded by the final state of the carry bit.

[June 13, 13, 13, 13, 2017, Arya Raychaudhuri, Santa Clara, California]

Obviusly, in this scheme, each sum digit is extracted every clock cycle, and the adder is recursively used for the next, and so on. The advantage is that only one adder is needed for this scheme, but the time taken to add multiple digits is number of digits times the clock period. A parallel scheme can be configured where multiple adders work simultaneously to add multiple digits in one clock period - fast, but needs more circuitry.

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Item#303> Direct decimal half subtractor (Item#s 302) simulated

[June 12, 12, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#302> Direct decimal half subtractor - a dual to  the half adder (Item#s 298, 301)

Please, note the duality from the difference in propagation of the wavefront as indicated by the yellow arrow in the middle. The data is fed to the left column (A*) in a normal way, but the wavefront propagation and the edge geneneration circuit  makes it look like added by 10, effectively, 6 as 16, 7 as 17 etc. The carry bit is initialized to 1 at the start, but goes to 0 if the sum register turns around (shifts) from 9 to 0

[June 12, 2017, Arya Raychaudhuri, Santa Clara, California]

An example position of the sum and carry registers shown for a case where 7-4=3. Note that the ctlout9lr is entered into the carry in such a way that it unsets on receiving a 0 edge, as opposed to set in the half adder case.

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Item#301> The edge generation circuit for the direct decimal half adder (Item#s298-300) expanded

Please, note that repetitive logic is represented by same color dots

[June 09, 2017, Arya Raychaudhuri, Santa Clara, California]

The difference in connection to the wavefront sensing AND gates on the right side (BP*) with respect to the left side (AP*) is to account for the fact that the time to update the 'qen' state is slower than the generation of the P*e edges. This can be seen by tracing the respective circuits.

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Item#300> Some more examples of direct decimal half adder (Item#s 298, 299) action  

[June 08,08, 2017, Arya Raychaudhuri, Santa Clara, California]

The half adder shows the advantage of using the advancing waveform scheme of Item#265 (qx>qy?) along    with   the clk-to-q bi-directional shift register that provides speed and miniaturization. The underlying principle being the edge based design methodology. The good thing about the edges is that they quickly accomplish a task and vanish, they don't linger - avoiding interference with other entities in time. The energy of an edge is given by VxIxdelta-t - since V is constant, the energy can always be adjusted with I and/or delta-t.

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Item#299> Simulation of the half adder of Item#298 - showing 7+6=13, 3 in sum, 1 in carry

Since this is just a half adder, and no shift is involved wih  the addendum regsiters, they were simply modeled as DC states (1V/0V). So 7 --> 0000000100, and 6-->0000001000. Only the result sum register (10 stages, 0-9) and the carry bit (1 stage) uses the clk-to-q  bi-directional  shift register (Item#258). The simulation result is shown below

[June 08, 2017, Arya Raychaudhuri, Santa Clara, California]

The left-most pane shows the advancing waveform introduced as a pulse in top left of the schematic of Item#298, through the series of AND gates. The second pane from the left shows the edges output when the latch is set (qen=1). Please, note that the p01e, p02e, p03e, etc. are same el9, el8, el7 ... of Item#298, taken in a monotonic sequence. The third pane shows the ORing of the edges p* to create the clk sequence pulsein1. Exactly the same number of clk edges are produced, as the sum of the two addenda. These clk edges (high frequency) drive the result shift register and carry bit, as shown in panes 4 & 5.

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Item#298> A direct decimal half adder schematic - the half adder will use the multiple clk edges as shown in Item#297

[June 06, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#297> Towards a direct decimal half adder - using the paradigm of the qx>qy circuit of Item#265, extracting edges out of an advancing pulse waveform, and running a 20-stage clk-to-q     bi-directional  shift register (Item#258) with the edges

[June 06, 2017, Arya Raychaudhuri, Santa Clara, California]

The multiple (20) edges (top pane) are getting extracted out of a 20ns pulse (P00). The the pulse edges correspond to a frequency of about 1.67GHz. So, we are pushing the shift register operation to the limit - but, still it can be made to work (bottom pane). The 20 stages of the shift register are pulsed through in about 12ns. P00 is advancing through a series of AND gates as in Item#265, and a +edge extractor at each stage  gets the edges out.

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Item#296> 'shft' edge (see Item#295) generation for a manually operated pgen (Item#238)

[June 04, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#295> Simulaion of the Reset Pulse duplicator circuit of Item#294 

The top panel shows the case where a 'shft' pulse sets the SEN latch - this leads to the shft-ed operation of the pgen. Please note that the duplicated pulse (resetout, top pane) is slightly thinner than the first pulse. This was a result of choosing R=100KOhms, C=150fF, Pvth0,LVT= -0.287V. By adjusting these design variables, one can achieve more desirable pulse width/spacing for the duplicated pulse. Although, it is not very vital since the vmon works with the rising edges - one more advantage of working with edges.



[June 02, 2017, Arya Raychaudhuri, Santa Clara, California]

The bottom panel shows the case where no 'shft' edge was received by the SEN latch - so no duplication of the first pulse occurs. This is the un-shft-ed case.

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Item#294> Reset pulse duplicator circuit for a shft-ed pgen that should produce 1 (un-shft-ed) or 2 (shft-ed) reset pulses for consumption by a shft-ed vmon (Item#290)

[June 03, 2017, Arya Raychaudhuri, Santa Clara, California]

One reset pulse (P1) generated by the pgen's inherent reset generator (see, for example, Item#286) gets duplicated to (P1 OR P2) when the SEN is high. The SEN is activated by a pulse 'shft' which needs to be generated by the shft-ed pgen's input circuitry when shft+Number are pressed.

The PE input to the P2L latch is generated by the inverted falling edge of the P2 pulse.

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Item#293> Spice input file used in the simulation of Item#292

[May 31, 2017, Arya Raychaudhuri, Santa Clara, California]

** The simulation was done using the PTM LP 45nm models for PMOS, NMOS, and on an LTSpice IV simulator

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Item#292> UpperCase LowerCase selector circuit (see Item#290) simulated - LCX, UCX generation. Uses the inverter-C timer of Item#291

Note the additional input terminal LC to the LCX generating AND gate (top right). This is needed to suppress an unwated LCX edge right after UCX falls to 0.

[May 31, 2017, Arya Raychaudhuri, Santa Clara, California]

The following sim panels show voltages on some of the important nodes in the above circuit. The top panel shows LCX selection, with one reset pulse coming in inside the timer delay, the bottom panel shows the UCX selection with two reset pulses coming in inside the timer delay

[May 31, 2017, Arya Raychaudhuri, Santa Clara, California]

Interestingly, the method can be generalized to a standalone pulse counter, by increasing the delay time and adding more latches.

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Item#291> inverter-C timer used in Item#290 simulated

Please, note that I had to use a 100KOhms resistor below the inverter to the left of C to accomplish the 70ns delay targeted. Again, the same PTM LP 45nm model (Item#268) was used for the simulation

[May 30, 2017, Arya Raychaudhuri, Santa Clara, California]

Please, also note the ~1.4ns delay of FR with respect to LC unsetting by Z. This ensures ~FR remains 0 when the final (end of monitoring) reset pulse's +edge comes in - protecting the latches from any conflicting inputs.

As indicated in Item#285, 100fF corresponds to 2.284x2.284 um^2 of gate cap - so, 350fF would be 8umx2.284um of gate cap. While a 100K resistor can be realized by a 50 squares long nwell resistor with 2K/square sheet rho. Or, through a mildly subthreshold nfet biased appropriately.

The resistor and the nfet above it dissipates a few uW of power roughly for the duration of time the capacitor discharges to 0. After that there is no dissipation during the rest of the monitoring time, although LC remains at 1 for the entire  time (delay + monitoring). Note in the following panel that if a typical longer monitoring time is chosen, the integral of V(vout).I(Rxx).dt is negligible when divided by the entire cycle time.

[May 30, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#290> "Shfted"  transmission gates vmon circuit edited from the vmon of Item#288

The changes with respect to the circuit of Item#288 are marked in yellow.

[May 28, 2017, Arya Raychaudhuri, Santa Clara, California]

Please, note the little timer involving the capacitor C, and the inverter to its left. The timer can expect one or two pulses (see Item#289)  within a small time interval, say 70ns. If there is just one pulse coming in, the lower latch (LC) is set, if there are two pulses coming in, both latches (LC,UC) are set. When C discharges to a low value, FR goes to 1, and looks for the states of LC, UC, and accordingly generates the lower case (LCX) and the upper case (UCX)  selectors used in the transmission gates at the bottom. FR initiates monitoring as usual. The reset pulse Z is being used to unset the latches (LC, UC) at the end of the cycle, when the final reset pulse is received.

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Item#289> "Shfted" transmission gates with the vmon of Item#288

One thing is obvious from the use of the reset pulses in the vmon - they are serving as commands to the system, and the clk pulses as the data, both tramsmitted on the same channel. For example, if we allow the first reset pulse to be a pair of two reset pulses, that is, you can send either one or two pulses right at the end of the clk pulses, we can let the single pulse open 15 separate transmission gates, while the pair open another 15 transmission gates. This is comparable to a 'shfted' operation of the vmon - where, sending a pair means pressing the 'shft' button after the clk pulses. 

[May 24, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#288> Vmon of Item#229 edited to receive the 1.8V positive reset pulses as output by the pgen of Item#286

Please, notice the small change in the yellow marked region near top left. The pulse height sensor of Item#287 has been represented by a special symbol. The AND gate at the top thickens the dip in vout, to create a thicker dip (X) that prevents the reset pulses from entering the clk line, ANDs them off.

[May 23, 2017, Arya Raychaudhuri, Santa Clara, California]

As was the case with the vmon of Item#229, the input to the inverter to the left of the +edge detect circuit needs to be a 1 to 0 dip for the reset pulses (at the vout node above), and the input to the clk line needs no other positive pulses than just the clk pulses coming from the pgen. In the case of Item#229, negative reset pulses were allowed into the clk line, as they would not move anything. But, in this case, the positive reset pulses needed to be cleaned up, before they could enter the clk line.

[May 23, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#287> Pulse height sensing between 0/1V and 0/1.8V pulses as generated by the pgen of Item#286

The nfet on the left and the resistor beneath it (common drain config) are being used to translate the input pulse amplitude down to vs0 level. The resistor helps provide the bias current for the nfet. If the resistor is too high or open, the bias current will be in the sub-threshold, and VG-vs0 << Vth, so vs0 will not be down enough, if the resistor is  too low, there will be more leakage. The 1MOhm resistor was found to give a vs0 of 0/0.866V pulse for vin of 0/1.8V, and 0/0.28V pulse for vin of 0/1V. The inverter on the right then translates the vs0 to 1/0 or flat 1V at vout - depending on vin of 0/1.8 or 0/1 respectively.



[May 22, 2017, Arya Raychaudhuri, Santa Clara, California]

The above core pulse amplitude sensor circuit will be used to edit  the vmon of Item#229 for positive reset pulses sensing. Please, note that the leakage currents are down enough to yield a power dissipation under 1uW.

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Item#286> Logic Level Shifter of Item#284 plugged into the pgen of Item#241 - turns the negative reset pulses into positive 1.8V pulses

Note the small changes in the pulses output circuit - marked in yellow at he top. While an 1.8V supply is needed, no deep nwell or capacitor is necessary. The level shifter is indicated by a special symbol.

[May 20, 2017, Arya Raychaudhuri, Santa Clara, California]

Simulation results for 1, 7, and 15 pulses are shown below as examples - the 1.8V reset pulses stand up as designed

[May 20, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#285> On the leakage current during vin=1V of the Logic level shifter of Item#284

Please, note in the following annotated circuit diagram that the Mn1 fet does not figure in the charging or discharging paths for the output capacitor. Its function is only to provide a leakage path so that the Mp0 fet can remain off during vout=0. Otherwise, vout would not be 0. So, Mn1's  W/L ratio can be reduced without affecting the vout waveform.

[May 19, 2017, Arya Raychaudhuri, Santa Clara, California]

Since, the above simulation uses a vin/vout duty cycle of ~0.5, the mean power dissipation is reduced from 16.2 uW to 1.8uW. For reset pulse or low duty cycle vin/vout, it will reduce further. For a duty cycle of 0.1, it will become 0.36uW - which is quite low. Please, note that there is no change in the vout waveform, going from case1 to case2.

Another factor is the W/L ratios of Mn0, Mp0, Mp1 - these have been kept adequate to drive a 100fF load cap. Reducing these aspect ratios would further reduce the steady-state power dissipation. In this 45nm PTM model used, the gate oxide thickness (toxe) is   1.8e-9 m (18 angstroms), the relative permittivity of the oxide material (epsrox) is 3.9. Vacuum dielectric constant being 8.85e-12 F/m, it can be shown that 100fF roughly equals a 2.283umX2.283um gate cap - this is a relatively large size compared to the fet sizes, indicating large fanout - more than 2500 45nmX45nm fets

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Item#284> Logic level shifting from 0/1V to 0/1.8V when an 1.8V supply is available

First making sure that the generic NMOS/PMOS fets with the PTM model are capable of working with an  1.8V supply

[May 18, 2017, Arya Raychaudhuri, Santa Clara, California]

Both the top pane (PMOS) and the bottom pane (NMOS) show that the fets can be operated up to 1.8V - since the test was done for 2V.

Now, the level shift circuit and its simulation are shown below

[May 19, 2017, Arya Raychaudhuri, Santa Clara, California]

The NMOS fets used for the simulation uses L=45nm W=45nm. The PMOS  fets used for the simulation uses L=45nm W=90nm. Please, note that there is a current path through the top PMOS and the left bottom NMOS when the vin is 1V, but for reset pulse applications, the vin is 1 only for a brief interval.

The above level shifter can be used to turn the negative reset pulses of the pgen (Item#241) into positive 1.8V pulses, as mentioned in Item#281.

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Item#283> Shell emulation of the JHC algorithm of Item#247 - runs the solarcell water level sense shell (Item#282) in the background mode

Three consecutive sweeps' results shown below. New data turns into the ref for the next sweep. Please, note that the top While loop is the solarcell background process (&). 

[May 09, 2017, Arya Raychaudhuri, Santa Clara, California]

This Item exemplifies how the shell based logic emulation first discussed in Item#38 also applies at the system/subsystem level.

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Item#282> Shell emulation of the solarcell water level sensor (Item#228) - a 10 stage example shown, for use wih the JHC circuit of Item#249

[May 08, 2017, Arya Raychaudhuri, Santa Clara, California]

Note that the waterlevel data string is getting simultaneously to a file 'waterlevel' which can be read in by a JHC emulator - the latter running in the foreground, and this then running in the background.

Please see how the water level is fluctuating in the figure below

[May 08, 2017, Arya Raychaudhuri, Santa Clara, California]

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Stressing the electroMechanics implications of the circuits discussed on this page ....

Item#281> Misc comments on the APC simulation of Item#279

From the simulation results, it is quite clear that between the staircasing and the pgen pulsing, the latter is slower. One idea can be to double the clock frequency (staircaser) and run the pgens with that. That will shink the pulsing time down.

The 'data' entry into the qd0 bit of the clk-to-q shift register (see Item#242) can be disabled by a latch/AND, the latch being set/unset by the apcon/apcoff pulses. To note is the fact that this 'data' entry/non-entry starts/stops the APC. The apcoff pulse can also  be autogenerated by a +edge of All LX* ORed in the pgen (Item#241). This way, one can run the APC in the unfolded mode (for example), for detecting just one voltage level, once in a while.

The scheme can be extended to sense and pulse out multiple electro-mechanical variables (vin's) - apcon-temperature, apcon-pressure, apcon-speed, etc. at periodic intervals. Now, let's say, we use the pulses for each sensed variable to populate latch clusters of the cruise control/JHC (Item#270,247,249) type columns. This way, we can get the +/- control pulses out for each sensed variable, from the respective twin columns.

If the negative demarcation pulses of the pgen are problematic for some applications, they can be replaced by high positive (~1.8V) pulses, with some circuit modifications

The PMOS voltage sense (Item#274) used in the APC for quantization error sensing could be used directly in some situations to sense normalized Vin, avoiding any comparator opamp/diffamp. Of course, that will be like regular AtoD conversion w/o qerror sense. To many, what's happening inside an opamp is a mystery, here you can see what's happening - you typically like what you understand!

***.

Item#280> Complete block diagram for the double pgen APC simulated in Item#279

[Apr 07, 2017, Arya Raychaudhuri, Santa Clara, California]

All components used in the above diagram were discussed in earlier Items, except for the push select circuits for sel* (quantization error). The push select circuits for s* were discussed in Item#s 244, 271. The push select circuits for the sel* are simpler. sel7 - push7 example shown below.

[Apr 07, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#279> Double pgen APC - one pulsing out the staircase level, and the other the quantization error (see Item#s 276-278)

Please see item#245, where I had  indicated three serial staircasings, followed by three parallel pulsing sequences. What I have achieved instead is one staircase, and simultaneous crunching of the quantization error (Item#278). While the two parallel pulsing sequences run in folded time. Trying to achieve the 0.001 level resolution (with three digits) would have introduced inaccuracies during combining levels, capacitive charging, etc. So, this two digits  approach. 

[Apr 07, 2017, Arya Raychaudhuri, Santa Clara, California]

In the leftmost pane, the states of the ladder-sweep shift register are shown. On the rightmost pane the staircase V(nXXr), is superimposed on the analog voltage levels V(vin). The staircase levels s* sensed and the quantization error levels sel* are also shown on this pane.  The second pane from left shows the pulsing of the staircase levels in folded time.  The second pane from right shows the parallel pulsing of the quantization error levels in folded time.

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Item#278> diffamp based comparator function for the APC (see discussion under Item#277)

VVIN1 vin 0 PWL (0 0.0005 50ns 0.0005  51ns .0995 100ns 0.0995 101ns 0.2005 150ns 0.2005 151ns 0.2995 200ns 0.2995 201ns 0.4 250ns 0.4 251ns 0.51 300ns 0.51+ 301ns 0.60 350ns 0.60 351ns 0.7005 400ns 0.7005 401ns 0.7995 450ns 0.7995 451ns 0.9005 500ns 0.9005)

VVIN2 nXXr 0 PWL (0 0.0 50ns 0.0  51ns 0.1 100ns 0.1 101ns 0.2 150ns 0.2 151ns 0.3 200ns 0.3 201ns 0.4 250ns 0.4 251ns 0.5 300ns 0.5+ 301ns 0.6 350ns 0.6 351ns 0.7 400ns 0.7 401ns 0.8 450ns 0.8 451ns 0.9 500ns 0.9)

[Mar 31, 2017, Arya Raychaudhuri, Santa Clara, California]

Please, note that when V(vin) - v(nXXr) >= 0.5mv the V(opout) = 1, otherwise, V(opout) is 0. This comparator function when integrated to the APC works fine - see below how the reconfigured (no opamp) comparator output V(opoutinst) [top pane] is triggered as soon as V(nXXr) equals or goes below V(vin) [bottom pane], and on its turn, generates the s* and sel* pulses [middle pane]:

[Apr 03, 2017, Arya Raychaudhuri, Santa Clara, California]

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Item#277> opamp and diffamp parallel configuration used in the simulation results of Item#276

[Mar 31, 2017, Arya Raychaudhuri, Santa Clara, California]

I had to adjust the Vth0 of the PMOS fets of the PMOS volt sense (Item#274) to -0.94V (from -1V), and also the PMOS source bias steppings changed to 0.075V from 0.080V, in order to get all the levels correctly.  So, at this point, we are using three PMOS vth0  values in the circuit - a high vth0 of -0.94V for the PMOS volt sense, a standard vth0 of -0.587V for all logic gates, and a low vth0 of -0.3V for the transmission gates  (see Item#269). For NMOS, we are using two vth0 values - a standard vth0 of 0.623V for all logic gates, and a low vth0 of 0.3V for the transmission gates (see Item#269).

In the next Item I will discuss a scheme that can emulate the comparator function of the opamp wih the addition of a bit of circuitry to the diffamp, in parallel with the PMOS volt sense.  This will totally eliminate the requirement of the opamp. But, the scheme will need the introduction of a super low vth0 (0.1V) NMOS device to the mix. The basic idea is to place the vout2 of the diffamp to the gate of a ~0 vt (small current defined vt) NMOS with a resistive load. When the vout2 is positive, the NMOS will conduct, otherwise, not.

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Item#276> diffamp (Item#273) and PMOS voltage sense (Item#274) integrated to the folded time APC of Item#271

This will enable achieving 100 quantization levels using just 10 staircase steps, a single opamp, and a diffamp with PMOS voltage sense. Achieving 1000 quantization levels as earlier indicated in Item#245 is over-ambitious.

[Mar 27, 2017, Arya Raychaudhuri, Santa Clara, California]

Please note that the left pane represents the sensed staircase levels, and the middle pane represents the sensed  Qerror levels. For examle, a level of 0.73V excites s8 (base level 7) and sel4 (base level 3). The sel* levels will be pulsed out using a parallel pgen circuit through corresponding push channel select circuits (similar to the one shown in Item#244 for the sensed staircase levels, s*).

The following zoom-in shows how the diffamp's vout1 and vout2 look at the time of readout (using the 'read' edge).  As is expected, the vout1 floors to ~0V, and the vout2 settles to a steady level near the middle of the *relevant* staircase step. The nature of vout1 & vout2 during all other staircase steps diverges from that under the target biasing situations simulated in Item#273, and is not relevant.

[Mar 27, 2017, Arya Raychaudhuri, Santa Clara, California]

The 'readpulse' generated from ~SxxAND of Item#244 unsets a latch, which is then set again by the falling edge of the clk signal in the middle of the staircase step. The rising edge of this latch's setting at that point is the 'read' pulse.

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Item#275> The output of the diffamp of Item#273 fed into the PMOS level sense of Item#274 - generates the pulses needed for the push channel select circuits (see Item#244) for the quantization errors

[Mar 27, 2017, Arya Raychaudhuri, Santa Clara, California]

Please, note that the 'read' pulses emulate the effect of a delayed inverted falling edge of ~SxxAND in Item#244. The 'read' pulse is added as an additional input to each AND gate of the XOR/AND structure in Item#274 - meant to read out the sensed level only when the diffamp outputs have flattened out. This avoids reading out spurious levels during the rising/falling shifts of the diffamp's  vout2.

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Item#274> A PMOS voltage sense to receive the amplified staircase differences of Item#273 - a simpler  variant of the multi-vt NMOS scheme of Item#272

[Mar 25, 2017, Arya Raychaudhuri, Santa Clara, California]

In this case, no negative biases and deep nwells are needed. A single high Vth of -1V, and gradually increasing source and bulk (nwell) biases, possibly from a relatively lower resistance potential divider, would do the trick. If we had gotten a gain of 10 from the diffamp of Item#273, these bias potentials would go up by 100mv at each step, but, I have kept the differences at ~80mV to account for the ~8.2 gain of the diffamp. The AND and XOR combination at the bottom is provided to account for the overlaps in the sensed level pulses dx*xor. For example, if the v(ggx) is such that both dx4xor and dx5xor can excite the next stage as a  "1" level, only the dx4xor will be chosen. This is the same logic as in Item#228.

The simulation results are shown below:

[Mar 25, 2017, Arya Raychaudhuri, Santa Clara, California]

Although this circuit is meant to sense the amplified quantization errors of the APC of Item#271, one can think of using it for large signal digital based amplifier or feedback. No opamp is being used.

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Item#273> APC Staircase (Item#271) quantization error amplification using a simple CMOS diffamp - the Vout2 is meant to be fed in as Vin of the multi-vt structure of Item#272

VVIN1 vin1 0 PWL (0 0.05 50ns 0.05  51ns .17 100ns 0.17 101ns 0.28 150ns 0.28 151ns 0.4 200ns 0.4 201ns 0.43 250ns 0.43 251ns 0.51 300ns 0.51+ 301ns 0.65 350ns 0.65 351ns 0.75 400ns 0.75 401ns 0.85 450ns 0.85 451ns 0.99 500ns 0.99)

VVIN2 vin2 0 PWL (0 0.0 50ns 0.0  51ns 0.1 100ns 0.1 101ns 0.2 150ns 0.2 151ns 0.3 200ns 0.3 201ns 0.4 250ns 0.4 251ns 0.5 300ns 0.5+ 301ns 0.6 350ns 0.6 351ns 0.7 400ns 0.7 401ns 0.8 450ns 0.8 451ns 0.9 500ns 0.9)

[Mar 23, 2017, Arya Raychaudhuri, Santa Clara, California]

Please, note that this is a test of the moving staircase levels  difference amplification - V(nXXr) of Item#271 corresponds to Vin2 here, and the V(vin) of Item#271 to Vin1 here. The biasing and the fet sizes have been adjusted to generate a ~0V floor for vout1, so that the vout2 represents the amplified quantization error. The amplification is reasonably linear with respect to the voltage differences, but the gain achieved is <10. So, the Vt's of the multi-vt structure need to be slightly lowered to account for the <10 gain here.

** The basic cmos diffamp: courtesy,  Analysis and Design of Analog Integrated Circuits, by PR Grey,PJ Hurst, SH Lewis, and RG Meyer

***

Item#272>  A multi-threshold NMOS level sense circuit for APC (Item#271) quantization error crunching ...

[Mar 21, 2017, Arya Raychaudhuri, Santa Clara, California]

 The 10 NMOS devices varying in Vt by 100mv can be generated from three generic Vth  values of 0.0V, 0.39V, 0.68V, and substrate biasing separate deep Nwell enclosures, as shown below

[Mar 21, 2017, Arya Raychaudhuri, Santa Clara, California]

In the below simulation results, the top panel shows the subthreshold curves for the 10 NMOS devices - note the 100MV Vt shifts. The second and the third panels show the results of   a DC sweep from 0 to 1V on vin

[Mar 21, 2017, Arya Raychaudhuri, Santa Clara, California]

The negative Vb biases needed for the deepNW enclosures can be obtained  from a resistors based potential divider out of a -2V or -1.8V bias produced on chip with an opamp (by inverting a positive voltage), or brought in from off chip. 

A similar scheme can also be drawn with PMOS devices on separate nwells - that way, we can avoid using deep Nwells and negative biases.

***

Item#271> Resistors ladder sweep staircasing and pgen pulse generation parallelized for the APC of Item#269

This helps in increasing the analog data sampling frequency - brings the sampling time down from 775ns to 504ns, for a 44MHz clock. When the sample sensing (staircasing) is going on for a particular data sample, the previous sensed level  (pushx) is getting pulsed out. Achieving roughly 2Mcycles/sec sampling rate in this case. The very first pulsing cycle is a dummy cycle producing just 1 pulse.

The main difference in the circuit involves retaining the sx levels till the end of the ongoing pulsing cycle, and letting the pushx get generated by the pgen reset pulse, instead of with qd10. Also, the data entry into the clk-to-q staircaser happens right after the pgen latch for pushx is set.

[Mar 16, 2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#270> Reconfiguring the JHC algorithm (Item#247) for control systems where you track a reference level, e.g. a driverless car cruising through different speed zones

Let's say, you are in a 45mph zone, transitioning into a 35mph zone. The new Ref  level is set for 35 by virtue of wireless signaling from the speed limit signs, and the car's actual speed is captured in the Data column - so you need to do relative data shift to get the speed back to 35, if fluctuations occur in speed, AND there are no obstacles in view.

[Mar 15, 15, 2017, Arya Raychaudhuri, Santa Clara, California]

Of course, in many cases, the pulses from the relative shift may not go to a stepper motor, but to some other voltage controlled device  through a pulses to analog converter such as in Item#166.

Why is the above algorithm slightly different from that of Item#247? Answer: you can post speed limits (or similar) to a driverless vehicle, but you cannot post level limits to water in the bay/lake.

***

Item#269> Containing the 'idle' undefined state of the transmission gates output in the APC ladder sweep of Item#243 - fixing it to 1V

[Mar 14, 2017, Arya Raychaudhuri, Santa Clara, California]

Simulation results for 10 levels (0.5, 1.5, ....9.5) to pulses [V(crpin)] conversion shown below

[Mar 14, 2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#268> Checking on the current voltage characteristics of the NMOS and PMOS fets (PTM 45nm) that were used in all the simulations so far ...

[Mar 09, 2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#267> On the versatility of the clk-to-q bi-directional shift register (Item#s 173, 258-264)

You can start a pulse train at any stage, stop anywhere, oscillate, fork, generate finite number of pulses from it, divide clock frequencies in a specifiable way,  run it in the counter mode for deep frequency divisions and binary interfacing, do decimal calculations with it and store decimal numbers, use it for sweeps, and so on ... an ultimate protocol cruncher! Also, you can easily convert it into a one-directional shift register (Item#172).

Bi-directional shift registers are not new, but, 50% gate count reduction is a striking feature of the clk-to-q shift. Because, it is getting so much smaller, and easy to hook up (as seen in earlier examples), more and more chip designs can use massive forks to accomplish tasks along the way. Various things happening at various locations of the maze, maybe, even at different frequencies. It's like townships (logic structures) building up along the banks of a flowing river, and getting things done.

***

Item#266> Simulation of the decimal digit compare circuit of Item#265

Three cases shown, top: qx6=1, qy5=1, middle: qy6=1, qx5=1, and bottom: qx5=1, qy5=1. Note the clipping of the advancing wavefront in the top and middle panels (top panes), as soon as the neq is set. But, in the bottom panel, since qx=qy, the neq is not set, and the wavefront goes through unclipped.

[Feb 25, 2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#265> A pulse driven circuit for comparing (qx>qy?) two decimal digits such as in Item#264

The following circuit works with a single square pulse entered through pulsein, to compare two columns of decimal bits [qx9, qx8, ....qx0] and [qy9,qy8,....qy0]. Checks to see if qx>qy. If qx=qy, neq=0, xgrty=0.  If qx>qy, neq=1, xgtry=1. If qy>qx, neq=1, xgtry=0. The checking takes place using the advancing wavefront of the pulse as it travels through the series of AND gates. As soon as neq is set, the pulse's journey stops. That means we have found the top most unequal bits, no need to look any further down ....

[Feb 24, 2017, Arya Raychaudhuri, Santa Clara, California]

The sequential pulse based checking requires much less circuitry than elaborate non-pulse based X>Y  checkers, and fast enough to be completed within a clock cycle. Also, if neq=0 at the end of the columns,  this can be used recursively to compare another pair of columns. Not just decimal digits where only one bit per column is 1, this can be used to compare any two ten bit  binary numbers.

***

Item#264>A decimal board for adding, subtracting, storing integers for inventory control inside or outside the chip - based on clk-to-q bi-directional shift registers (Item#258)

The transparent green arrow shows LR (add) shifts, and the transparent yellow arrow shows the RL (subtract) shift

[Feb 22,  2017, Arya Raychaudhuri, Santa Clara, California]

The board is initialized to 000 by applying the inverse of the delayed falling edge of the reset pulse through p00, p01, p02. Once initialized the board will keep adding and subtracting in response to incoming pulses (clk) which can come from  a latch cluster based pgen such as in Item#170. Following simulation results show the cases where 235 pulses are added (LR=1, RL=0), and then 235 pulses are subtracted (RL=1, LR=0). To note is the fact that the above three digit decimal board is clamped at 999 and 000 for the highest and the lowest numbers.

[Feb 22, 22, 2017, Arya Raychaudhuri, Santa Clara, California]

In the top panel, the initial  state was 000, and in the bottom panel, it was 235. Of course, you can start at any numerical state between 000 and 999. To make the highest number 999999, you need to add three more shift registers, etc.

***

Item#263> An asynchronous counter out of the clk-to-q bi-directional shift register of Item#258

Note how groups of two register stages are being used to half the input frequency, and drive the next duo.

[Feb 19,  2017, Arya Raychaudhuri, Santa Clara, California]

Simulation results indicate clear counter action

[Feb 19,  2017, Arya Raychaudhuri, Santa Clara, California]

Obviuosly, this counter arrangement is not as fet-count friendly as the clk-to-q T-flipflop based Counter in Item#184, but, this has value from the  one shift register type can do it all premise. Also, this counter involves some interesting logical synthesis.

***

Item#262> N specifiable  2N frequency divider using clk-to-q bi-directional shift register of Item#258

[Feb 18,  2017, Arya Raychaudhuri, Santa Clara, California]

Simulation results for three cases where N=3, N=5, and N=8 are shown below. Please note the frequency divisions by 6, 10, 16 by counting the qqxx pulses within the space of the frequency divided LR time periods

[Feb 18,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#261> clk-to-q shift forking (see Item#257) involving a bi-directional shift register (Item#258) shown with a Left to Right shift example

[Feb 16,  2017, Arya Raychaudhuri, Santa Clara, California]

In the above diagram, only the ctlout4lr is forked into right and bottom routes. In order to make the joint totally forked, similar forking circuitry will need to be added for ctlout5rl, and ctlout5rlf2. Simulation of the above diagram is shown below for three cases, top: F1=1, F2=0, middle: F1=0, F2=1, bottom: F1=1, F2=1. For all the three cases, LR=1, RL=0, meaning, we are only looking at Left to Right shift

[Feb 16,  2017, Arya Raychaudhuri, Santa Clara, California]

Please, note that in some generalized fork situations, LR, RL states will need to be swapped/localized just before the forks happen.

*** 

Item#260> FET sizes used in the gates used to build the stages simulated in Item#s 258,259

.SUBCKT NAND4shift in1 in2 in3 in4 out vdd vss                          MN1 out in1 midx vss NMOS L=0.09um W=0.045um                  MN2 midx in2 midx2 vss NMOS L=0.09um W=0.045um              MN3 midx2 in3 midx3 vss NMOS L=0.09um W=0.045um            MN4 midx3 in4 vss vss NMOS L=0.09um W=0.045um                MP1 out in1 vdd vdd PMOS L=0.09um W=0.09um                      MP2 out in2 vdd vdd PMOS L=0.09um W=0.09um                      MP3 out in3 vdd vdd PMOS L=0.09um W=0.09um                      MP4 out in4 vdd vdd PMOS L=0.09um W=0.09um                   .ENDS

.SUBCKT NAND3shift in1 in2 in3 out vdd vss                              MN1 out in1 midx vss NMOS L=0.09um W=0.045um                  MN2 midx in2 midx2 vss NMOS L=0.09um W=0.045um              MN3 midx2 in3 vss vss NMOS L=0.09um W=0.045um                MP1 out in1 vdd vdd PMOS L=0.09um W=0.09um                      MP2 out in2 vdd vdd PMOS L=0.09um W=0.09um                      MP3 out in3 vdd vdd PMOS L=0.09um W=0.09um                   .ENDS

.SUBCKT RSLX in1t in2t in3t in1b in2b in3b out outbar vdd vss  XNAND_1 in1t in2t in3t outbar out vdd vss NAND4shift        XNAND_2 in1b in2b in3b out outbar vdd vss NAND4shift           .ENDS

.SUBCKT shiftstage pulsein  din setdlr setdrl resetdlr resetdrl          + sysreset LR RL qd qdbar ctloutlr ctloutrl vdd vss                    XRSLX setdlr setdrl din resetdlr resetdrl sysreset qd qdbar vdd vss RSLX                                                                              XNANDLR  qd pulsein LR ctloutlr vdd vss NAND3shift            XNANDRL  qd pulsein RL ctloutrl vdd vss NAND3shift               .ENDS

 Xbit0 pulsein1 p0 vdd ctlout1rl ctlout0lr ctlout0rl sysreset LR RL qq0 qq0bar ctlout0lr ctlout0rl vdd vss shiftstage                                Xbit1 pulsein1 p1 ctlout0lr ctlout2rl ctlout1lr ctlout1rl sysreset LR RL qq1 qq1bar ctlout1lr ctlout1rl vdd vss shiftstage                        Xbit2 pulsein1 p2 ctlout1lr ctlout3rl ctlout2lr ctlout2rl sysreset LR RL qq2 qq2bar ctlout2lr ctlout2rl vdd vss shiftstage                        Xbit3 pulsein1 p3 ctlout2lr ctlout4rl ctlout3lr ctlout3rl sysreset LR RL qq3 qq3bar ctlout3lr ctlout3rl vdd vss shiftstage                        Xbit4 pulsein1 p4 ctlout3lr ctlout5rl ctlout4lr ctlout4rl sysreset LR RL qq4 qq4bar ctlout4lr ctlout4rl vdd vss shiftstage                        Xbit5 pulsein1 p5 ctlout4lr ctlout6rl ctlout5lr ctlout5rl sysreset LR RL qq5 qq5bar ctlout5lr ctlout5rl vdd vss shiftstage                        Xbit6 pulsein1 p6 ctlout5lr ctlout7rl ctlout6lr ctlout6rl sysreset LR RL qq6 qq6bar ctlout6lr ctlout6rl vdd vss shiftstage                        Xbit7 pulsein1 p7 ctlout6lr ctlout8rl ctlout7lr ctlout7rl sysreset LR RL qq7 qq7bar ctlout7lr ctlout7rl vdd vss shiftstage                        Xbit8 pulsein1 p8 ctlout7lr ctlout9rl ctlout8lr ctlout8rl sysreset LR RL qq8 qq8bar ctlout8lr ctlout8rl vdd vss shiftstage                        Xbit9 pulsein1 p9 ctlout8lr vdd ctlout9lr ctlout9rl sysreset LR RL qq9 qq9bar ctlout9lr ctlout9rl vdd vss shiftstage

* Model Definition

45nm PTM LP model V2.1 (Arizona State University)

** Simulation tool used

LTspiceIV V4.23l

The transistor sizes are model and tech node dependent, since relative delays are involved.

***

Item#259> Bi-directional (left to right, and right to left) clk-to-q shift register of Item#173 simulated for edge enties as in Item#254 (not data train as in Item#258)

Both LtoR and RtoL panels shown below. In both cases, the edge was entered at p5, with all other inputs held at 1 at all times. To note are the ctlout* edges generated in each case, and also the mounts and dismounts of the qqx states

[Feb 15,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#258> Bi-directional (left to right, and right to left) clk-to-q shift register of Item#173 simulated

[Feb 15,  2017, Arya Raychaudhuri, Santa Clara, California]

Left to right shift with LR=1, RL=0. data train ~datain entered through p1, all other px held  at 1

[Feb 15,  2017, Arya Raychaudhuri, Santa Clara, California]

Right to left shift with LR=0, RL=1. data train ~datain entered through p9, all other px held  at 1

[Feb 15,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#257> Advantages of the clk-to-q shift registers (Item#s 172,173,174) are many ...

The small size of the individual stages helps the Moore's law. They can be easily hooked up, as the previous examples involving the one-directional shift stages show - amenable for serial and parallel data entry and data read. One thin clock edge can drive many stages. A bi-directional shift register can be adapted to multiple  2N frequency divider applications, keeping I0 (see Item#254) up while shifting left, and down while shifting right. Also, the small stage size creates the possibility of register mazes allowing various chess-rook shift patterns, as shown below.

[Feb 12,  2017, Arya Raychaudhuri, Santa Clara, California]

Borrowing the concept of shunting in railway tracks - logically opening and closing sub-routes.

***

Item#256> The clk-to-q shift re-explained  - how it takes advantage of the finite gate delays that are inevitable and unavoidable at any tech node, and turns them into a positive player in circuit compaction

[Feb 14,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#255> What about the reset pulse for the excerpted pulses in Item#254, to mark the end of excerption?

It's basically the envelope pulse I0 sent out in a side channel. Interestingly, I0 can also be used to observe/replicate the dataflow at any point in the circuit for the requested number (n) of clock cycles, by ANDing  I0 with the potential of that point. It's like excerpting the flow of a river, as shown below.

[Feb 11,  2017, Arya Raychaudhuri, Santa Clara, California]

where T is the period of the clock pulses.

***

Item#254> Clock pulses excerption in the pgen mode using the clk-to-q register, requesting 1-10 pulses by selection

In Item#253 pulse thickening was done using excerption from the home made oscillator (RC-XOR based), the input being the thin edges from a circuit like the JHC (see Item#s 248-249).

But what if you want to excerpt the requested number (1-10) of pulses like in a pgen (Item#155) from the system clock? Here is a way to do it. More than 10 pulses can be requested by using decimal clusters such as in Item#170.

[Feb 10,  2017, Arya Raychaudhuri, Santa Clara, California]

Note that the Clock Gen is just the system clock available in all digital systems (microchips).  Again, like in Item#253, we have three latches, L0, I0, M0 with similar functions. The excerpted pulses (clkexcerpt) are put out by ANDing the clk with I0. In the below panels, I have shown 3 cases where 10, 1 , and 5 pulses were requested, as examples.

[Feb 10,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#253> Excerpting pulses out of a free running pulse train - a variant of the scheme shown in Item#250

[Feb 09,  2017, Arya Raychaudhuri, Santa Clara, California]

Please, note that I have added a new stage, qq10 to the clk-to-q shift register. This stage is set by the +edge of the oscstart pulse, and is meant to remain  always set for the entire course of the free pulses run, because this stage now drives the oscillator charging/discharging cycles. I have also added three more latches, L0, I0, and M0 to control the process of excerption.

[Feb 09,  2017, Arya Raychaudhuri, Santa Clara, California]

The four excerpted pulses are shown in the top pane, the next pane shows the free running pulses. The sequence of events should also be clear from the above panel. First, the oscstartej happens, to start the oscillator. Next the readoutej starts the XOR sweep (see Item#249) - giving rise to, let's say, four edges that are getting mounted to the qqxx register (third pane above). The qd10 +edge (ending the XOR sweep) sets the L0 latch to let the next pulseins  enter the register as pulsein1.

The first pulsein1 sets the latch I0 to mark the start of pulse excerption.  Exactly four pulsein1s enter, the last one coinciding with the falling edge of qq9 - sets the M0 latch, indicating that we are to excerpt only one more pulse. And. that pulse's falling edge resets the L0 and I0 latches - stopping pulsein1s and excerption, leaving qq10 at 1, to continue the oscillations. Please, also note the dismounts of the qqxx states in the third pane - this indicates proper data shifts through the clk-to-q shift register.

***

Item#252> The Ka 0 sense circuit used in Item#250 expanded

It's simply two inverters in series - the first inverter uses an ultra high Vth (-0.95V) PMOS, and the second uses an ultra high Vth (0.95V)  NMOS. Note that the first inverter's rise time is kept slow using longer channel length, narrow width for the PMOS, and higher load cap coming from the second inverter's regular PMOS. This way, it is possible to detect a very low voltage  on Ka, around 19mV. The third inverter is just a regular one isolating the 0 sense inverters from the +edge sense circuit.

[Feb 05,  2017, Arya Raychaudhuri, Santa Clara, California]

An important thing to note is  that the 0 sense circuit typically will not sense the absolute 0. So, since the charging cycle for the first pulse starts from 0, the succeeding ones start from the low 0 sensed value. So, the first pulse is slightly thicker.

The following simulation result where the pulse thickener circuit was run in a free running oscillator mode (not letting the pulsein get into the clk-to-q register), while the succeeding pulses measured 1us thick, the first pulse was 2ns thicker.

[Feb 07,  2017, Arya Raychaudhuri, Santa Clara, California]

Now, is it possible to excerpt a few pulses, a finite series, from the free running pulses, leaving out the first pulse? We will explore that later.  Probably a pulse generator without using counters can also emerge!

***

Item#251> Taking care of the signpulse (Item#249) into the circuit of Item#250 - changes and additions

[Feb 09,  2017, Arya Raychaudhuri, Santa Clara, California]

The shaded regions are where changes and additions happen with respect to Item#250.

***

Item#250> Thickening a finite series of very thin pulses (pulse edges) into large pulse width pulses - e.g., the series of thin edges (allpulses) that come out in the sim results of Item#248

This is accomplished with the following circuit that includes a clk-to-q shift register that queues up the incoming thin edges in the descending bits (qq9, qq8, qq7 ... etc.). At the end of the train of pulse edges, one by one, the bits are pushed out to the qq9, and thickened with the help of an RC-XOR circuit. 

[Feb 09,  2017, Arya Raychaudhuri, Santa Clara, California]

The qd10 +edge and the readout +edge come from Item#249. The circuit was simulated with R1=1KOhms, R2=10KOhms, C1=100pf, C2=100pf - to get pulse widths of roughly 1us, while the 4 incoming thin edges are only 0.5ns wide. The top panel is a zoomin of the early part of the second,  that shows the 4 incoming edges, and how they are getting sequentially mounted to the clk-to-q shift register. The second panel shows the charging-discharging cycles, the clk-to-q shifts, and, of course, the KXout thick output pulses.

[Feb 03, 05,  2017, Arya Raychaudhuri, Santa Clara, California]

Various combinations of R1,C1,R2,C2 can give different pulse widths.

***

Item#249>The entire JHC circuit that was simulated for the results in Item#248, includinhg the data readout triggered XOR sweep pulses generation by a clk-to-q shift register

The shaded portion in the top panel (below) indicates the relative shift control circuitry for the stage 9. There will be nine more such swept by +edges of qd1, qd2, ...qd9

[Feb 01, 01,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#248> Simulation results for a variant of the JHC circuit of Item#246

While the simulation demanded a number of implemenational changes with respect to the circuit of Item#246, the main difference is that I am now using simple interconnected latches instead of the clk-to-q shift registers for the data and Ref columns (see Item#247). The actual circuit simulated will be described later. The clk-to-q shift register (qd0-qd10)  is only used to generate the XOR sweep pulse edges, and the reset pulse.  The use of simple latches for the data and the Ref columns saves the clk-to-q shifter  NAND gates - reducing transistor counts.

The top panel shows the case where the data bit qs4 is higher than the Ref bit qr0 - note that 4 (4 - 0) pulses (red) come out in the top pane, preceded by a pink sign pulse (goes into a signpulse channel). 

[Jan 31,  2017, Arya Raychaudhuri, Santa Clara, California]

The bottom panel shows the case where the Ref bit qr6 is higher than the data bit qs1.  Again, in the top pane, 5  (6 - 1) pulses (in light blue) come out, but no sign pulse this time. 

***

Item#247> The algorithm behind  JHC circuit of Item#246 explained ....

[Jan 27,  27, 2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#246> Jetty Height Control (JHC) circuit with regard to the amphibian transportation scheme discussed in Item#s 225-228

[Jan 27,  2017, Arya Raychaudhuri, Santa Clara, California]

Since the sensor (solar cell) outputs are already quantized, this two shift registers (one for new sensor data, the other for memorizing the last height)  approach is applicable. There is a third shift register (not shown in this diagram) that is supplying the sequential clock and the reset pulse. The scheme (item#242) for APC ladder sweep can be used for that purpose. The JHC circuit is yet to be simulated.

***

Item#245> On quantization error of the APC of Item#244

Since the entire voltage range of 1V is divided into 10 equal intervals, the maximum difference between a sampled level (Vin) and the sensed level of the staircase can be 0.1V. But, this error can be reduced by the scheme shown in Item#189 (the circuit needs some changes) by recursively using the same ladder and sensing scheme for the three significant digits, and retaining the push channel levels in the three latch clusters. When the three recursive ladder sweep cycles are over, simultaneously start three parallel pgens to pulse out the three significant digits.  On the PAC side, three vmons would receive the three significant digits and combine them. This way, the quantization error can be reduced to 0.001V.

[Jan 24,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#244> Push channel select circuit and full APC simulation showing the sensing and pulsing for three different voltage levels (0.65V, 0.35V, 0.85V) - continued from Item#s 240-243

[Mar 14,  2017, Arya Raychaudhuri]

qd* pulses come from Item#242, and are shown in the top plot. As soon as the ladder sweep (Item#243) is done, the integrated pgen (Item#241) pulses out the selected channel (shown in green, top plot).   

The bottom plot shows the ladder sweep output staircase superimposed on the sensed voltage level (Vin). Also the respective channel select latch states along with the push* pulses are shown.

The APC is run using the clock shown in Item#240.

***

Item#243> APC resistors ladder sweep with the shift register sweep pulses of Item#242 

[Jan 23,  2017, Arya Raychaudhuri, Santa Clara, California]

Please, note the sweep voltage staircase at the nXXr node. Since a steady sample voltage of 0.65V was applied to the Vin non-inverting input of the opamp, the opamp output (opout) sharply rises to 1 when the staircase level descends below 0.65V.  Next we will convert the level sense to an appropriate push channel of the pgen.

***

Item#242> Getting into the analog to pulse converter (APC, more appropriate name than ADC of Item#163) - the voltage levels sweep circuit and the pulsing scheme shown

Making some changes here with respect to the conceptual schematic of Item#163. From 15 quantization levels to 10 - requiring the pgen (Item#241) to put out a maximum of 10, and a minimum of 1 pulses. The top inverter delay chains for voltage levels sweep are now replaced with a clock synced clk-to-q Left to right shift register (10+1 stages), first discussed in Item#172. The last stage output (qd10) is used for level read at the end of the sweep, and activating the appropriate channel of the pgen.

[Jan 22,  2017, Arya Raychaudhuri, Santa Clara, California]

In order to look at the clock synchronization of the sensing schme and the pgen following it, the qd10 is simply turned to push10 of the pgen, as a place holder. The details of the level sensing will be simulated later. Please, note that the data (a pulse) is entered in a clock synchronized way into the left most stage of the shift register. Then, with each clock pulse, the data shifts right. So, each of qd0, qd1, qd2 .....qd9 can be used to activate the level sweep transmission gates of Item#163. The APC is started with a start pulse as shown. The apcout state enables the sweep, it s brought to 0 by the pgen start, and again brought back to 1 at the rising edge of the pgen's second reset pulse. This way, the cycle continues in sync with the clock ... Here is a simulation

[Jan 22,  2017, Arya Raychaudhuri, Santa Clara, California]

The simulation shows three cycles of voltage levels sweep immediately followed by pulse generation. Please, note that the shift register works with the clock's + edge - one good thing about working with thin clock pulses is that you don't need to fix hold time issues.

***

Item#241> Pgen for system integration (e.g. Item#164) with 2 reset pulses upgrade, both auto generated (no push buttons)

[Jan 20,  2017, Arya Raychaudhuri, Santa Clara, California]

As with the manual reset pgen, 1-15 pulses are generated depending on which channel is pulsed from a previous stage. Channel4 input stage is shown as an example. Unlike the manual reset button pgen (Item#230), the toggle is not turned off until the final auto-generated reset pulse.

Please, note that the final reset pulse is getting generated at state 32 (31+1) of the counter. An example simulation generating 15 pulses shown below. The simulation uses the oscillator of Item#240 for clock pulses. 

[Jan 20,  2017, Arya Raychaudhuri, Santa Clara, California]

The cycle extends from the begining of the first pulse, till the end of the last reset pulse - relevant for the purpose of estimating sampling rates etc.

***

Item#240> An RC coupled NOR latch oscillator working with the pgen (Item# 239) to supply the free running clock pulses

[Jan 19,  2017, Arya Raychaudhuri, Santa Clara, California]

Simulation results for push15 with the clkout (above) used as the clock for the pgen

[Jan 19,  2017, Arya Raychaudhuri, Santa Clara, California]

Please note from the top figure that the average power consumption of the pgen with the clk generator embedded is about 50uW.

***

Item#239> Simulation results for the dual reset pulse pgen (Item#230) with all later updates (Item#s 236, 237, 238) showing generated pulses and pgenbusy led bias

The push buttons are being pressed in simulation through PWL waveforms applied to a NFET (mimics the blue spring push button), there is another NFET below that, whch is operated by the pgennotbusy bias. So is also the red reset button simulated with an NFET. The pulsing scheme is given below

[Jan 18,  2017, Arya Raychaudhuri, Santa Clara, California]

The results of three pushes, push1, push7, and push15 are given below, superimposed by the pgenbusy bias pulse

[Jan 18,  2017, Arya Raychaudhuri, Santa Clara, California]

There were minor implementational adjustments (sizing of gates, resistance values, etc) while doing the simulation.

***

Item#238> Push button edge detect must for dual reset pulse pgen (Item#s230, 236,237), also circuitry for single press ON double press OFF led indication, when needed (corresponding to vmon upgrade of Item#232)

[Jan 17,  2017, Arya Raychaudhuri, Santa Clara, California]

Relevant parts of the design shown.

Since the first reset pulse is auto generated, it comes quickly, hence the push button's lift-up needs to be sensed.

With the single press ON double press OFF led indication shown at the bottom of the push button circuitry, first push of the push button leaves the led ON, a second push turns it OFF. Reminds the user which button(s)  was/were pressed once.

***

Item#237> Dual reset pulse pgen (Item#s230, 236) uses the reset button to release the pgen for fresh push button press, pgen busy  indicator led

Now, no new push button press will  start a  new pulse generation cycle until the red reset button is pressed. Also, a pgen busy indicator LED is added

[Jan 16,  2017, Arya Raychaudhuri, Santa Clara, California]

Only relevant parts of the design shown.

***

Item#236> Detailed connection considerations more than  offset the FETs reduction in the scheme discussed in Item#s 233-235 - a new scheme shown

Detailed connections of the pgen follwing the scheme of Item#233, would require the LX and ~LX lines split between the flipflops Q1 - Q4 (the Qx0 can directly connect to ~Q0). So, that will need 4 pairs of transmission gates per push button. A calculation shows that while 210 FETs are reduced in the new scheme, 264 new transistors will need to be added. Hence the scheme of Item#233 is only of academic interest.

Another scheme, more competitive than the previous one is shown below - this will add only 120 FETs, leading to a net reduction by 90 FETs

[Jan 16,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#235> Bare-bones simulation check for the transmission gates scheme of Item#s 234.235

[Jan 15,  2017, Arya Raychaudhuri, Santa Clara, California]

A simulation check involving two latches lx1 and lx2 getting set at different times, and a free flowing pules train on q0, shows proper output  (selx) of the channel selection AND, and no leakage (except for switching currents) through the Mp and Mn FETs of the left and the right transmission gates associated with [q0, ~q0]. The bare-bones circuit shown above, and the simulation results shown below.

[Jan 15,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#234> Understanding the transmission gates scheme of Item@233

When a particular latch associated with a push button is set (output of the upper NAND gate is 1), the two transmission gates next to it are ON (low resistance path), and their outputs are clearly defined (1/0). Also, X is 1, ~X is 0. Hence, the bottom transmission gates associated with [Qx, ~Qx] are all ON. Between the left and the right transmission gates associated with [Qx, ~Qx], one is clearly OFF, and the other is clearly ON, depending on the connection to their gates. This is determined by whether Qx or ~Qx needs to be fed to the channel selection AND gate, for this push button. 

When all latches are unset (output of the upper NAND gate is 0), the two transmission gates next to it are OFF (open), and their outputs are *not* clearly defined. Because of that there could be an unpredictable low resistance path between Qx and ~Qx in some situations. But, since X is 0, and ~X is 1 when the latches are all unset, the bottom transmission gates associated with [Qx, ~Qx] are all OFF - cutting off that possible low resistance path. Also, since X input to the channel selection AND gate is 0, we don't care about the other inputs. 

Now, why are the two transmission gates associated with each latch needed? In order to decouple an unset  latch's outputs from those of another latch that may be set.

***

Item#233> Size reduction (lesser number of FETs) of the pgen of Item#230 

Only relevant parts of the design where size reduction happens are shown in the following figure

[Jan 12,  2017, Arya Raychaudhuri, Santa Clara, California]

Only the shaded portion is repeated for the 15 push buttons.

***

Item#232> Selective circuit block activation/deactivation using an on-chip voltage monitor (Item#229) used in an applicator mode

The augmentation of the single reset pulse voltage monitor (Item#150)  to the two reset pulses upgrade (Item#229) leads to a "single press ON, double press OFF" switch as shown in the following diagram. Now, by pressing the push button 4 on the pulse generator of Item#230, you can turn on the CIRCUIT 4 in the chip. Immediately press the Reset button of the pgen to release the vmon for possible activation of another circuit block, let's say, CIRCUIT 7. Again pressing the Reset button releases the vmon. So, at this time, you have activated both CIRCUIT 4 and CIRCUIT 7. You can do more if needed. A second press of the push button 4/7 followed by Reset button switches off the respective circuit block.

[Jan 10,  2017, Arya Raychaudhuri, Santa Clara, California]

One important advantage of the above scheme over that of Item#160 is that you can now have multiple circuit blocks simultaneously activated. Note that the FR of Item#229 is being used to generate the ON/OFF pulse using the Slow Inverter/AND duo. The pulse is then being fed to the voltage monitor pin that transmits it through the transmission gate onto the switch for CIRCUIT 4.

***

Item#231> Simulation results showing the improvement in the vmon of Item#229 (using two reset pulses) over the original circuit of Item#150, using a single reset pulse

[Jan 10,  2017, Arya Raychaudhuri, Santa Clara, California]

Note that we have kept a free flowing pulse train on Channel4, and two dc biases on Channel2 and Channel3 (top plot)

The next plot shows the case of the original vmon (Item#150), the instantaneous 1s of the channel selection AND gates are not suppressed for channels 2, 3, and the voltage monitor pin momentarily  sees the Channel2 and Channel3 voltages. This may not be an issue for voltage monitoring purposes, but, will definitely cause problems in more general applications.

The third plot shows the result for the vmon of Item#229 using two reset pulses. There is no unwanted pick up of the Channel2 and Channel3 voltages on the way to Channel4.

***

Item#230> Companion pgen upgrade for the vmon upgrade  (2 reset pulses) of Item#229

[Jan 11,  2017, Arya Raychaudhuri, Santa Clara, California]

An example simulation result showing the case for channel4 pulses shown below. The first reset pulse indicating the end of the pulse train is auto generated, the second is the manual (push button) reset pulse.

[Jan 09,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#229> Before getting back on to the Jetty height control, here is an important upgrade to the vmon (Item#150) - introducing a second reset pulse right after the pulse train

As discussed in Item#s 211 and 212, a pulse rectifier could flatten the pulse train into a thick pulse which (inverse of it being fed to the channel selection AND gate of the vmon) could be used to stop the instantaneous openings of the "previous" channels. But, we can avoid the pulse rectification by simply introducing a second pulse train demarcating reset pulse into the picture. We would then use the following pulse scheme for a channel4 activation.

[Jan 08,  2017, Arya Raychaudhuri, Santa Clara, California]

The corresponding vmon upgrade will look like:

[Jan 10,  2017, Arya Raychaudhuri, Santa Clara, California]

Please note that the first reset pulse does not reach the Reset line, it just sets the latch to 1 (FR). The FR fed to the channel selection AND gate remained 0 till after the last pulse of the pulse train - so, no "previous" channels would open when favorable states were presented to their inputs as the pulses came by. 

We want to make sure that the FR, ~FR states do not change before the inverted reset pulse beyond the deep Nwell switch and the next inverter subsides. This is accomplished by first  thinning the inverted reset pulse using  a commonly used edge sense ckt (dynamic emulation code shown in Item#207). and then feeding them to the latch states gated NANDs - the second thinned reset pulse passing through the lower of these is inverted towards the Reset line.

Next we will discuss how the pulse train demarcaing reset pulse is auto generated by an upgrade to the  pgen of Item#155.

***

Item#228> Water level detection is the first step to Jetty height control (Item#227) - a solar cells based scheme with visual led display 

[Jan 06,  2017, Arya Raychaudhuri, Santa Clara, California]

The XOR and AND gates are meant to select the lower solar cell's Voc (~0.5V)  if more than one cell is activated by the floating light source. For solar cell physics, please see Item#143.  The Vth of the Nfets in the XOR, AND gates should be < Voc.  The gates can be run at 1.1V VDD. 

The floatable  light source  has the ring to help insert it on to the solar cells column. For easy removal, there is a thin magnetic strip that allows a magnet tipped rod to pull it out when the batteries die. The light proof external box has two small holes - one at the bottom for water entry, and the other at the top for air exit. This avoids any sudden disturbance to the water level inside the box due to waves in the lake. The internal enclosure containing the solar cells and the wires is heremetically sealed, and made of an opaque marerial, except for the light-entry apertures in front of the solar cells.

***

Item#227> Flatboat  exterior and height adjustable Jetty schematic for the ambhibian transportation (Item#s 225, 226) 

[Jan 05,  2017, Arya Raychaudhuri, Santa Clara, California]

Approximate flatboat top surface area 10x15 sq feet. When a 1500 kg car rides on the boat, the boat is pushed down into the water by 4-5 inches. The 4000 kg ballast helps keep the center of gravity of the loaded boat sufficiently below the water - needed to avoid a capsize. Note the boat's under water taper towards the ballast - this ensures sufficient underwater depth to accommodate the propeller and the rudders. The fluid dynamic nose reduces water resistance while the boat moves forward. The boat's interior is empty except the propeller and rudders control mechanisms shown in Item#226. The boat is made of some light but strong material.

The Jetty height above the water level must remain constant in order to ensure smooth ramping of the car  into and out of the boat. The hydraulic press operated Jetty is lifted or lowered in response to the water level every hour or so. This is accomplished by the Jetty height control mechanism.

***

Item#226> Propeller and Rudder control for the flatboat (Item#225) carrying the Car with the amphibian upgrade 

[Jan 04,  2017, Arya Raychaudhuri, Santa Clara, California]

***

Item#225> A possible application of dual Electro-Magnetic spring shaft (Item#221) - a car on boat driving the boat beneath

[Dec 29,  2016, Arya Raychaudhuri, Santa Clara, California]

One dual electro-magnet spring shaft can help switch power from the car's wheels to the propeller and back, and another from the steering control from the car's axle to the Rudder of the boat and back.

***

Item#224> What happens when you brake the vehicle running at, let's say, the 4th gear (refer to Item#223)?

The action of braking is required to generate a pulse. This pulse can be used to take the transmission immediately to Neutral. (not shown in Item#223). This is needed to remove power  from the output power chain (Item#222), and reduce load on the brakes. When the speed of the vehicle has sufficiently reduced, put it to a lower gear (1,2,3).  Note from the diagram of Item#223, that you can switch to any of the foward gears from Neutral.

At the time of switching to a forward gear, two possibilities exist. One, that the speed of the output chain is higher than the speed of the output pawl of the gear you are switching into. The chain will slip on the pawl until speeds become equal. Two, the chain speed is lower than the speed of the pawl. The pawl will immediately engage, and start bringing the chain to its speed.

***

Item#223> control circuit for a press-button manual transmission based on the dual Electro-magnetic spring shaft system (Item#222) - it generates the pulses to activate the left and bottom electro-magnets. No stick shift or clutch pedal are needed for this manual transmission.

[Dec 15, 2016, Arya Raychaudhuri, Santa Clara, California]

When the car is started, the car start pulse pushes the system to Neutral. You can go to Gear1 only if the previous state was zero speed, or Neutral,or Gear2. Otherwise, the Gear1 switch press will do nothing. Similarly, you can go to Gear2 only when the previous state was Gear1, Gear3, or Neutral. And, so on. Any successful Gear press will first deactivate the previous state, and the 'led'for the new Gear state will glow.

As soon as a Gear change takes place, the pulse B to energize all the bottom electro-magnets is generated using the RC circuit on top left - the second from top. The RC time constant determines the width of the pulse B which releases all Cantilevers to their ground state, by briefly pulling the Button-head rod down (Item#221). 

As soon as the B pulse goes to zero, the RC circuit for the C pulse starts discharging - helping generate the C pulse to activate the Gear specific Cantilever electo-magnet. But , the C pulse is fed to the Gear's electro-magnet only when B has gone to Zero - this is accomplished by the transmission gates to the right of the Gear latches (~B.GX1, ~B.GX2, etc).

See that the reverse gear can only operate when the speed was Zero. When the speed goes from finite to zero, Z goes from 0 to 1 - this +edge  deactivates the reverse gear.  The sane +edge will also push the system to Neutral, and release the B pulse to all the bottom electro-magnets. The Neutral state is deactibvated by any successful Gear changes.

***

Item#222> dual Electro-magnetic spring shaft (Item#221) based transmission with the reverse gear included - upgraded from Item#204

[Dec 15, 2016, Arya Raychaudhuri, Santa Clara, California]

Note that I have transposed the output power chain (Item#204) to the left of the output pawls, making the upward direction of the output power chain the  forward drive mode. This was done to accommodate the reverse gear.

One important point about the reverse mode operation is that all the unpowered forward pawl shafts will rotate, as pulled by the downard moving output chain. But, that's okay - because they are unpowered. In the above diagram, the 2nd gear is shown engaged, all others are off.

***

Item#221> Electro-magnetic spring shaft (Item#203) goes CMOS - no steady state power loss

[Dec 13, 2016, Arya Raychaudhuri, Santa Clara, California]

Note that a bevel is added to the bottom side of the cantilever's electromagnet end. When the electromagnet gets an electric pulse, it pulls the cantilever, and the bevel pushes the buttonhead of the spring added buttonhead rod down and beyond it. Immediately, the buttonhead moves up and holds the bevel from returning. This is smilar to how the runner on an umbrella pole is kept from moving down by the top spring. 

At the time of release, the bottom electromagnet is energized wih a pulse, the butonhead rod is pulled down, instantly releasing the bevel enhanced cantilever.

** The cylinder is nothing but a ball bearing whose outer wheel is moving in the groove of the encasement. The gear shaft snugly fits into the hole of the inner  wheel of the ball bearing. On the left side of the outer wheel the cantilever  is welded, and on the right side, the spring. The spring's other end is welded to the encasement. While the outer wheel translates, the inner rotates

***

Item#220> Shorting through Poly undetected by an LVS deck

Recently, while working with a client, I had discovered some incorrect booleans/connects in an LVS deck they were using  - leading to undetection of potential shorts through accidental Contacts falling  on the Gate region.  See the following figure



[Oct 10, 2016, Arya Raychaudhuri, Santa Clara, California]

The short between GATEnet and Xnet due to the "unintended contact" was not coming out. Why? This type of booleans will not get it out:

::::

::::

COND_POLY = POLY NOT SILICIDE_BLOCK

GATE = COND_POLY AND DIFF

CONT_POLY = COND_POLY NOT GATE

:::

CONNECT M1 CONT_POLY BY CONT

CONNECT GATE CONT_POLY

:::

You cannot break a  process conducting layer into pieces, and then connect to some pieces. Proper booleans:

 :::

::::

::::

COND_POLY = POLY NOT SILICIDE_BLOCK

GATE = COND_POLY AND DIFF

:::

CONNECT M1 COND_POLY BY CONT

CONNECT GATE COND_POLY

:::

Although there may be some DRC checks that prevent Contacts on Gate, an LVS deck should be self-sufficient to detect connectivity issues. Also, what if the special DRC check is suppressed in some aggressive IP layouts...

***

Item#219> How to make sure that fullchip LVS would not pass with some under-lying Vias missing - see issue II. discussed in Item#113

In this deck, create a special text layer, let's say, 726 (or any layer number that did not already occur in the deck) for reading in the bump text pieces. Attach the 726 to the bump opening (BO) layer, and declare it as a port text layer. Then CONNECT BO to APRDL

Create a variant of the LVS deck for fullchip runs

Obviously, in the bump text file, edit any pre-existing text layer number (probably corresponding to APRDL layer) to 726

Comment out all other TEXT LAYER read-ins, ATTACHments, port text declarations

That's it! This is the LVS deck to use , for fullchip LVS. This will ensure that 

1. Only text read in are the bump text pieces - that's how the chip connects to the outside world

2. The Bump Openings are present for each bump

3. No under-lying Via layers are missing

-------

One way to avoid creating a new text layer (726) and deleting all other text readins/attach in the deck is to create a dummy cover cell (probably, with calibreDRV) and instantiate the FullChip under it at (0,0).  Now call the dummy cover cell FullChip_cover.  In the bump text file, change the cell name of the top cell to FullChip_cover.

In the LVS deck, you have to change the ATTACHment of the APRDL texting layer from APRDL to the BO layer, and also add 

CONNECT BO to APRDL 

as before. Note that the dummy cover cell pushes down all text except for the APRDL texting as in the bump text file. So, all non-bump text turns out to be lower level text now, for LVS.  

--------

One important thing to note is  that at fullchip LVS time, any top level (of hierarchy)  texting on the chip represents an electrical connection from outside. So, reading in any top texting other than bump text  means you are not modeling it correctly. Because the probe package can only probe the APRDL through the BO! If the connection  model is incorrect, the LVS results are not reliable.

***

Item#218> Automatic shut-off car seat warmer switch



[Apr 21, 2016, Arya Raychaudhuri, Santa Clara, California]

The switch is turrned On by pushing and releasing the blue "On button"; and turned off in two ways, either by getting off of the seat, releasing the blue "Body press" button, or by pushing and releasing the red "Off button". This way, the seat can be heated up even before entering the car, as is sometimes needed in winter times. And, the shutting off is automatic as you move out, removing the chance of unwanted battery bleed.

The concept of logically energizing and deenergizing parallel electrical connections using mechanical spring connect buttons can be useful in other situations too. Detailed simulation yet to be done.

***

All snippets presented here are strictly proprietary to LVS DEBUG SOLUTIONS LLC, any commercial use of these is prohibited, without proper distribution agreement with the owner



Arya Raychaudhuri

[the dates added to the drawings and plates indicate last edit dates]

This "code snippets2" page is a continuation of the "code snippets" page. 

- parallel mode direct decimal full Adder

- sequential mode direct decimal full Adder

- direct decimal half Subtractor

- direct decimal half Adder

- high frequency AND pipe edges

- shft-ed operation of pgen & vmon

- positive 1.8V reset pulse pgen & vmon

- Shell emulation of JHC algorithm 

- Diffamp and ~0 vt nfet based voltage  comparator to replace opamp comparator

- PMOS volt sense circuit

- Folded time APC with Qerror crunching based on diffamp-PMOS volt sense

- Driver-less car control mechanism, a variant of JHC 

- A pulse wavefront driven x>y checker circuit, for binary numbers compare

-Shift Register based frequency divisions and Counter

- Shift Register forking

- Bi-directional clk-to-q shift register simulation

- clk-to-q shift register based resistors ladder sweep in APC simulation

- RC-latch and RC-XOR Oscillators, clock pulses generator

- Pulses Excerption from free running clock pulses

- Thin pulse thickening Circuit and Simulation

- Solar Cell based lake water level Monitor

- Jetty Height Control Circuit and Simulation

- simultaneous multiple chip sub-blocks activation/deactivation using pgen,vmon

- FET count reduction in pgen 

- dual reset pulse pgen, vmon

- Amphibian transportation model

- Auto-shut off carseat warmer switch

- Concept of a full-chip LVS deck

- CMOS (Dual ElectroMagnetic) spring shaft

- Manual transmission based on Dual ElectroMagnetic spring shaft