LVS DEBUG SOLUTIONS LLC

Spice_Code for TelEx3line (Item#403)

TelEx3-Line

.SUBCKT AND2 in1 in2 out vdd vss

MN1 out1 in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 vss vss NMOS L=0.045um W=0.135um

MP1 out1 in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out1 in2 vdd vdd PMOS L=0.045um W=0.27um

MN3 out out1 vss vss NMOS L=0.045um W=0.135um

MP3 out out1 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT NAND2BIG in1 in2 out vdd vss

MN1 out in1 midx vss NMOS L=0.045um W=0.54um

MN2 midx in2 vss vss NMOS L=0.045um W=0.54um

MP1 out in1 vdd vdd PMOS L=0.045um W=1.08um

MP2 out in2 vdd vdd PMOS L=0.045um W=1.08um

.ENDS

.SUBCKT NAND2 in1 in2 out vdd vss

MN1 out in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 vss vss NMOS L=0.045um W=0.135um

MP1 out in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out in2 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT NAND3 in1 in2 in3 out1 vdd vss

MN1 out1 in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 midx2 vss NMOS L=0.045um W=0.135um

MN3 midx2 in3 vss vss NMOS L=0.045um W=0.135um

MP1 out1 in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out1 in2 vdd vdd PMOS L=0.045um W=0.27um

MP3 out1 in3 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT AND3 in1 in2 in3 out vdd vss

MN1 out1 in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 midx2 vss NMOS L=0.045um W=0.135um

MN3 midx2 in3 vss vss NMOS L=0.045um W=0.135um

MP1 out1 in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out1 in2 vdd vdd PMOS L=0.045um W=0.27um

MP3 out1 in3 vdd vdd PMOS L=0.045um W=0.27um

MN4 out out1 vss vss NMOS L=0.045um W=0.135um

MP4 out out1 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT NAND_AND3 in1 in2 in3 out1 out vdd vss

MN1 out1 in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 midx2 vss NMOS L=0.045um W=0.135um

MN3 midx2 in3 vss vss NMOS L=0.045um W=0.135um

MP1 out1 in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out1 in2 vdd vdd PMOS L=0.045um W=0.27um

MP3 out1 in3 vdd vdd PMOS L=0.045um W=0.27um

MN4 out out1 vss vss NMOS L=0.045um W=0.135um

MP4 out out1 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT AND4 in1 in2 in3 in4 out vdd vss

MN1 out1 in1 midx vss NMOS L=0.045um W=0.135um

MN2 midx in2 midx2 vss NMOS L=0.045um W=0.135um

MN3 midx2 in3 midx3 vss NMOS L=0.045um W=0.135um

MN4 midx3 in4 vss vss NMOS L=0.045um W=0.135um

MP1 out1 in1 vdd vdd PMOS L=0.045um W=0.27um

MP2 out1 in2 vdd vdd PMOS L=0.045um W=0.27um

MP3 out1 in3 vdd vdd PMOS L=0.045um W=0.27um

MP4 out1 in4 vdd vdd PMOS L=0.045um W=0.27um

MN5 out out1 vss vss NMOS L=0.045um W=0.135um

MP5 out out1 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT NOR3 in1 in2 in3 out vdd vss

MN1 out in1 vss vss NMOS L=0.045um W=0.135um

MN2 out in2 vss vss NMOS L=0.045um W=0.135um

MN3 out in3 vss vss NMOS L=0.045um W=0.135um

MP1 out in1 midx vdd PMOS L=0.045um W=0.27um

MP2 midx in2 midx2 vdd PMOS L=0.045um W=0.27um

MP3 midx2 in3 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT NOR2 in1 in2  out vdd vss

MN1 out in1 vss vss NMOS L=0.045um W=0.135um

MN2 out in2 vss vss NMOS L=0.045um W=0.135um

MP1 out in1 midx vdd PMOS L=0.045um W=0.27um

MP2 midx in2 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT OR2 in1 in2  out1 vdd vss

MN1 out in1 vss vss NMOS L=0.045um W=0.135um

MN2 out in2 vss vss NMOS L=0.045um W=0.135um

MP1 out in1 midx vdd PMOS L=0.045um W=0.27um

MP2 midx in2 vdd vdd PMOS L=0.045um W=0.27um

XINV out out1 vdd vss INV

.ENDS

.SUBCKT NOR_OR2 in1 in2  out out1 vdd vss

MN1 out in1 vss vss NMOS L=0.045um W=0.135um

MN2 out in2 vss vss NMOS L=0.045um W=0.135um

MP1 out in1 midx vdd PMOS L=0.045um W=0.27um

MP2 midx in2 vdd vdd PMOS L=0.045um W=0.27um

XINV out out1 vdd vss INV

.ENDS

.SUBCKT INV0 in1 out vdd vss

MN4  out in1 vss vss NMOS L=0.045um W=0.09um

MP4  out in1 vdd vdd PMOS L=0.045um W=0.18um

.ENDS

.SUBCKT INV in1 out vdd vss

MN4  out in1 vss vss NMOS L=0.045um W=0.135um

MP4  out in1 vdd vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT INVSLOW in1 out vdd vss

MN4 out in1 vss vss NMOS L=0.45um W=0.045um

MP4 out in1 vdd vdd PMOS L=0.45um W=0.09um

.ENDS

.SUBCKT INVSLOW2 in1 out vdd vss

MN4 out in1 vss vss NMOS L=0.18um W=0.045um

MP4 out in1 vdd vdd PMOS L=0.18um W=0.09um

.ENDS

.SUBCKT pushbutton pushx Qin1 Qin2 Qin3 Qin4 edgein pgb QRSX QX1 QX2 QX3 QX4 vdd vss

R4push vdd RSXin 1000000

M4push RSXin pushx pbx vss NMOS L=0.045um W=0.135um

Xinvedge1p RSXin RSXin edge1p vdd vss NAND2

Xinvedge3p edge1p edge1p edgex1p vdd vss NAND2

Xinvedge4p edgex1p edgex1p edgex2p vdd vss NAND2

Xnandedgep edgex2p RSXin  RSXinedge vdd vss NAND2

X1RSXNAND2 RSXinedge QRSXbar QRSX vdd vss NAND2

X2RS4NAND2 edgein QRSX QRSXbar vdd vss NAND2

MNTXQ1 QX1 QRSX Qin1 vss NMOS L=0.045um W=0.045um

MPTXQ1 QX1 QRSXbar Qin1 vdd PMOS L=0.045um W=0.09um

MNTXQ2 QX2 QRSX Qin2 vss NMOS L=0.045um W=0.045um

MPTXQ2 QX2 QRSXbar Qin2 vdd PMOS L=0.045um W=0.09um

MNTXQ3 QX3 QRSX Qin3 vss NMOS L=0.045um W=0.045um

MPTXQ3 QX3 QRSXbar Qin3 vdd PMOS L=0.045um W=0.09um

MNTXQ4 QX4 QRSX Qin4 vss NMOS L=0.045um W=0.045um

MPTXQ4 QX4 QRSXbar Qin4 vdd PMOS L=0.045um W=0.09um

MNpb pbx pgb vss vss  NMOS L=0.045um W=0.135um

.ENDS

.SUBCKT TFF T q qbar clk reset vdd vss

X1AND3 T qbar clkbar mo1 vdd vss AND3

X2AND3 T q clkbar mo2 vdd vss AND3

X1NAND2 clk clk clkbar vdd vss NAND2

X2NAND2 T T Tbar vdd vss NAND2

X1AND2 Tbar q qTbar vdd vss AND2

X2AND2 Tbar qbar qbarTbar vdd vss AND2

X1NOR3 mo1 qTbar mqbar mq vdd vss NOR3

X2NOR3 mo2 qbarTbar mq mqbar vdd vss NOR3

X3AND2 mq clk so1 vdd vss AND2

X4AND2 mqbar clk so2 vdd vss AND2

X3NOR3 so1 qbar reset q vdd vss NOR3

X1NOR2 so2 q qbar vdd vss NOR2

.ENDS

.SUBCKT levelShift vin vout vdd18 vss

Mn0 vout vin vss vss NMOS L=0.045um W=0.135um

Mn1 vmid vin vss vss NMOS L=0.45um W=0.045um

Mp0 vout vin vmid vdd18 PMOS L=0.045um W=0.27um

Mp1 vmid vin vdd18 vdd18 PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT INV18 in1 out vdd18 vss

MN4 out in1 vss vss NMOS L=0.045um W=0.135um

MP4 out in1 vdd18 vdd18 PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT PLUSej XX XXej vdd vss

XINV XX XXdlay vdd vss INVslow

XINV1 XXdlay XXdlay1 vdd vss INVslow

XINV2 XXdlay1 XXdlay2 vdd vss INVslow

XAND XX XXdlay2 XXej vdd vss AND2

.ENDS

.SUBCKT XGATE Ngate XX XXout vdd vss

XINVselxxx Ngate Ngateinv vdd vss INV0

MNX4vm XXout Ngate XX vss NMOS L=0.045um W=0.135um

MPX4vm XXout Ngateinv XX vdd PMOS L=0.045um W=0.27um

.ENDS

.SUBCKT XGATEsmall Ngate XX XXout vdd vss

XINVselxxx Ngate Ngateinv vdd vss INV0

MNX4vm XXout Ngate XX vss NMOS L=0.045um W=0.045um

MPX4vm XXout Ngateinv XX vdd PMOS L=0.045um W=0.09um

.ENDS

.SUBCKT clkgen clkout vdd vss

MNclk cbiasbar cbias vss vss NMOS L=0.045um W=0.45um

MPclk cbiasbar cbias vdd vdd PMOS L=0.045um W=0.9um

MNclk1 cbiasLX cbiasbar vss vss NMOS L=0.045um W=0.45um

MPclk1 cbiasLX cbiasbar vdd vdd PMOS L=0.045um W=0.9um

XNORLX1 CbiasLX clkoutbar clkout  vdd vss NOR2

XNORLX2 Cbiasbar clkout  clkoutbar vdd vss NOR2

Cclk Cbias vss 100pf

Rclk vdd Xdrain 1000

MNTX1clk Xdrain clkout Cbias vss NMOS L=0.045um W=0.45um

MPTX1clk Xdrain clkoutbar Cbias vdd PMOS L=0.045um W=0.9um

MNTX2clk Cbias clkoutbar vss vss NMOS L=0.045um W=4.5um

.ENDS

.SUBCKT PGEN push1 push2 push3 pushreset1 crpin vdd vss vdd18

Xclkgen clkout vdd vss clkgen

X0TFF T0 Q0 Qbar0 clkout edge3 vdd vss TFF

X1TFF Q0 Q1 Qbar1 clkout edge3 vdd vss TFF

XQ2AND2 Q0 Q1 T2 vdd vss AND2

X2TFF T2 Q2 Qbar2 clkout edge3 vdd vss TFF

X1NOR5 QRS1 QRS2 X1NOR2out vdd vss NOR2

X2NOR5 QRS3 vss X2NOR2out vdd vss NOR2

X3NAND2 X1NOR2out X2NOR2out ALLRSout vdd vss NAND2

X1AND4 Qbar0 QX1 QX2 ALLRSout Selch vdd vss AND4

XNORoutLX1 Selch NORLXoutbar NORLXout vdd vss NOR2

XNORoutLX2 edge3 NORLXout NORLXoutbar vdd vss NOR2

XANDQ0out NORLXout Q0 Q0out vdd vss AND2

XT0AND2  vdd ALLRSout CR1bar T0 vdd vss AND3

XINVT0 T0 T0bar vdd vss INV0

XNANDpushSense1 T0bar pgennotbusyx PSx vdd vss NAND2

XNANDpushSense2 cr1bar PSx pgennotbusyx vdd vss NAND2

XANDpgennotbusy pgennotbusyx cr1bar pgennotbusy vdd vss AND2

*Vpgb pgennotbusy 0 DC 1

Xpb1  push1 Q1 Qbar2 Qbar3 Qbar4 edge2 pgennotbusy QRS1 QX1 QX2 QX3 QX4 vdd vss pushbutton

Xpb2  push2 Qbar1 Q2 Qbar3 Qbar4 edge2 pgennotbusy QRS2 QX1 QX2 QX3 QX4 vdd vss pushbutton

Xpb3  push3 Q1 Q2 Qbar3 Qbar4 edge2 pgennotbusy QRS3 QX1 QX2 QX3 QX4 vdd vss pushbutton

R1reset vdd CR1 1Meg

M6reset CR1 pushreset1 vss vss NMOS L=0.045um W=0.135um

XINVreset CR1 CR1bar vdd vss INV

XINVslowreset1 CR1bar CR1bardlay vdd vss INVslow

Cslowreset1 CR1bardlay 0 40ff

XANDreset1 CR1bar CR1bardlay pushresetup vdd vss AND2

XINVslowreset2 CR1 CR1dlay vdd vss INVslow

Cslowreset2 CR1dlay 0 40ff

XANDreset2 CR1 CR1dlay pushresetdn vdd vss AND2

X_ORpushrset  pushresetup pushresetdn pushreset vdd vss OR2

R4reset vdd CR 1Meg

M4reset CR pushreset vss vss NMOS L=0.045um W=0.135um

M5reset CR Selch vss vss NMOS L=0.045um W=0.135um

XNAND2reset CR CR CRbar vdd vss NAND2

XINVslow2 CRbar CRbardlay vdd vss INVslow

Cslow2x CRbardlay 0 40ff

XAND2reset2 CRbar CRbardlay resetX vdd vss AND2

MP1reset resetbar resetX vdd vdd PMOS L=0.045um W=0.135um

MN1reset resetbar resetX vss vss NMOS L=0.045um W=0.09um

Xin0reset resetbar resetin vdd vss INV0

Xlevshft resetin resetPP vdd18 vss  levelShift

XINV18  resetPP resetRR vdd18 vss INV18

MNTX1 Q0out resetPP CRpin vss NMOS L=0.045um W=0.045um

MPTX1 Q0out resetRR CRpin vdd18 PMOS L=0.045um W=0.09um

MNTX2 resetRR resetRR CRpin vss NMOS L=0.045um W=0.045um

MPTX2 resetRR resetPP CRpin vdd18 PMOS L=0.045um W=0.09um

Xinvedge1 resetbar  edge1 vdd vss INVslow

Xnandedge edge1 resetbar  edge2 vdd vss NAND2big

Xinvedge2 edge2 edge2 edge3 vdd vss NAND2

.IC V(Q0)=0 V(Q1)=0 V(Q2)=0 V(CR)=1 V(CRbar)=0 V(CRbardlay)=1 V(reset)=0 V(CRpin)=0 V(edge2)=1 V(edge3)=0

+ V(QRS4)=0 V(ALLRSout)=0   V(Cbias)=0 V(clkout)=0 V(pushreset)=0 V(NORLXout)=1

+ V(QRS1)=0 V(QRS2)=0 V(QRS3)=0

.ENDS

* VMON

.SUBCKT VMON crpin sel1 sel2 sel3 dialup phup resetpulse ANYsel vdd vss

* 1V 1.8V sorter, telephone up/down versus pulse train end sorter

Mn0 vdd crpin vs0 vss NMOS L=0.45um W=0.09um

R0 vs0 0 1Meg

Mninv vout  vs0 vss vss NMOS L=0.045um W=0.09um

Mpinv vout  vs0 vdd vdd PMOS L=0.045um W=0.09um

Xinvdlay1 vout voutx vdd vss INVSLOW

Xinvdlay2 voutx vouty vdd vss INVSLOW

Xor2 vouty vout voutthick vdd vss AND2

Xclkdlay1 crpin clkx vdd vss INVSLOW

Xclkdlay2 clkx clky vdd vss INVSLOW

Xclkout clky voutthick clkline vdd vss AND2

XresetNAND2  vout vout reset vdd vss NAND2

Xinvedge1 reset  edgex2 vdd vss INVslow

Xnandedge edgex2 reset edge3 vdd vss AND2

XNANDsel edge3 FRbar LatchIN1x vdd vss AND2

XANDreset edge3 FR LatchIn2x vdd vss AND2

*Xinvreset LatchIn2 LatchIn2 resetpulse vdd vss NAND2

Xinvlxin1x LatchIN1x LatchIN1 vdd vss INV0

Xinvlxin2x LatchIN2x LatchIN2 vdd vss INV0

Xinvreset LatchIn2 resetpulse1 vdd vss INV

Xinvreset2 resetpulse1 resetpulse2 vdd vss INVslow

Xinvreset3 resetpulse2 resetpulse3 vdd vss INVslow

Xorreset4 resetpulse3 resetpulse1 resetpulse vdd vss OR2

X1NANDlat LatchIN1 FRbar FR vdd vss NAND2

X2NANDlat LatchIN2 FR edge2clk FRbar vdd vss NAND3

Xinvedge1clk clkline edgex2clk vdd vss INVslow

Xandedgeclk edgex2clk clkline edge2clkp vdd vss AND2

Xnandedgeclk edge2clkp edge2clkp edge2clk vdd vss NAND2

XINVedge3_1 edge3 edge3inv1 vdd vss INVslow2

XINVedge3_2 edge3inv1 edge3inv2 vdd vss INV

XINVedge3_3 edge3inv2 edge3inv vdd vss INV

XNANDlx1 edge2clk dialupbar dialup vdd vss NAND2

XNANDlx2 edge3inv dialup dialupbar vdd vss NAND2

X_OR2 FR dialup phup vdd vss OR2

* Sorter ends here

*T0 set to vdd

X0TFF vdd Q0 Qbar0 clkline resetpulse vdd vss TFF

X1TFF Q0 Q1 Qbar1 clkline resetpulse vdd vss TFF

X1AND4ch1 Q0 Qbar1 FR Sel1 vdd vss AND3

*Xch1bar Sel1 Sel1 Sel1bar vdd vss NAND2

X1AND4ch2 Qbar0 Q1 FR Sel2 vdd vss AND3

*Xch2bar Sel2 Sel2 Sel2bar vdd vss NAND2

X1AND4ch3 Q0 Q1 FR Sel3 vdd vss AND3

*Xch3bar Sel3 Sel3 Sel3bar vdd vss NAND2

XORQ0Q1 Q0 Q1 ANYQ vdd vss OR2

XANDANYSel ANYQ FR ANYsel vdd vss AND2

.IC V(Q0)=0 V(Q1)=0 V(FR)=0 V(FRbar)=1 V(resetpulse)=0

+ v(clkline)=0 V(phup)=0 V(dialup)=0

.ENDS

.SUBCKT LINEx push1 push2 push3 pushreset sel1 sel2 sel3 dialup phup resetpulse crpin  ANYsel vdd vss vdd18

XPGEN1 push1 push2 push3 pushreset crpin vdd vss vdd18 PGEN

XVMON1 crpin sel1 sel2 sel3 dialup phup resetpulse  ANYsel vdd vss VMON

.ENDS

** LINE Output edges and inverses

*-------LINE1---------

XLINE1 vss push12 push13 pushreset1 sel1 sel12 sel13 dialup1

+ phup1 resetpulse1 crpin1  ANYsel1 vdd vss vdd18 LINEx

Xpejsel12 sel12 sel12pej vdd vss PLUSej

Xpejsel13 sel13 sel13pej vdd vss PLUSej

Xpejphup1 phup1 phup1pej vdd vss PLUSej

Xpejdialup1 dialup1 dialup1pej vdd vss PLUSej

Xresetpulseinv1 resetpulse1 resetpulse1bar vdd vss INV

*----------LIN2--------

XLINE2 push21 vss push23 pushreset2 sel21 sel2 sel23 dialup2

+ phup2 resetpulse2 crpin2  ANYsel2 vdd vss vdd18 LINEx

Xpejsel21 sel21 sel21pej vdd vss PLUSej

Xpejsel23 sel23 sel23pej vdd vss PLUSej

Xpejphup2 phup2 phup2pej vdd vss PLUSej

Xpejdialup2 dialup2 dialup2pej vdd vss PLUSej

Xresetpulseinv2 resetpulse2 resetpulse2bar vdd vss INV

*-----------LINE3-------

XLINE3 push31 push32 vss pushreset3 sel31 sel32 sel3 dialup3

+ phup3 resetpulse3 crpin3  ANYsel3 vdd vss vdd18 LINEx

Xpejsel31 sel31 sel31pej vdd vss PLUSej

Xpejsel32 sel32 sel32pej vdd vss PLUSej

Xpejphup3 phup3 phup3pej vdd vss PLUSej

Xpejdialup3 dialup3 dialup3pej vdd vss PLUSej

Xresetpulseinv3 resetpulse3 resetpulse3bar vdd vss INV

**busy detect and engage/disengage

XL1OR 12_21 13_31 L1busyinv L1busy vdd vss NOR_OR2

XL2OR 12_21 23_32 L2busyinv L2busy vdd vss NOR_OR2

XL3OR 13_31 23_32 L3busyinv L3busy vdd vss NOR_OR2

XL1busyor phup1 L1busy L1busyorbar L1busyor vdd vss NOR_OR2

XL2busyor phup2 L2busy L2busyorbar L2busyor vdd vss NOR_OR2

XL3busyor phup3 L3busy L3busyorbar L3busyor vdd vss NOR_OR2

XNAND12sel sel12pej L2busyorbar  sel12ej vdd vss NAND2

XNAND13sel sel13pej L3busyorbar  sel13ej vdd vss NAND2

XNAND21sel sel21pej L1busyorbar  sel21ej vdd vss NAND2

XNAND23sel sel23pej L3busyorbar  sel23ej vdd vss NAND2

XNAND31sel sel31pej L1busyorbar  sel31ej vdd vss NAND2

XNAND32sel sel32pej L2busyorbar  sel32ej vdd vss NAND2

XNANDlx12_21_1 sel12ej sel21ej 12_21bar 12_21 vdd vss NAND3

XNANDlx12_21_2 resetpulse1bar resetpulse2bar 12_21 12_21bar vdd vss NAND3

XNANDlx13_31_1 sel13ej sel31ej 13_31bar 13_31 vdd vss NAND3

XNANDlx13_31_2 resetpulse1bar resetpulse3bar 13_31 13_31bar vdd vss NAND3

XNANDlx23_32_1 sel23ej sel32ej 23_32bar 23_32 vdd vss NAND3

XNANDlx23_32_2 resetpulse2bar resetpulse3bar 23_32 23_32bar vdd vss NAND3

** dialtoner

XL1bzinvej L1busyinv L1bzinvej vdd vss PLUSej

XL1bzinvejpup L1bzinvej phup1 L1bzinvejpup vdd vss AND2

XANDp1upnotbz phup1pej L1busyinv p1upnotbz vdd vss AND2

XNORlx1_dtoner1 p1upnotbz L1bzinvejpup dtoner1 dtoner1bar vdd vss NOR3

XNORlx2_dtoner1 dialup1pej resetpulse1 dtoner1bar dtoner1 vdd vss NOR3

Xgatedtoner1 dtoner1 dtone spkr1 vdd vss Xgatesmall

XL2bzinvej L2busyinv L2bzinvej vdd vss PLUSej

XL2bzinvejpup L2bzinvej phup2 L2bzinvejpup vdd vss AND2

XANDp2upnotbz phup2pej L2busyinv p2upnotbz vdd vss AND2

XNORlx1_dtoner2 p2upnotbz L2bzinvejpup dtoner2 dtoner2bar vdd vss NOR3

XNORlx2_dtoner2 dialup2pej resetpulse2 dtoner2bar dtoner2 vdd vss NOR3

Xgatedtoner2 dtoner2 dtone spkr2 vdd vss Xgatesmall

XL3bzinvej L3busyinv L3bzinvej vdd vss PLUSej

XL3bzinvejpup L3bzinvej phup3 L3bzinvejpup vdd vss AND2

XANDp3upnotbz phup3pej L3busyinv p3upnotbz vdd vss AND2

XNORlx1_dtoner3 p3upnotbz L3bzinvejpup dtoner3 dtoner3bar vdd vss NOR3

XNORlx2_dtoner3 dialup3pej resetpulse3 dtoner3bar dtoner3 vdd vss NOR3

Xgatedtoner3 dtoner3 dtone spkr3 vdd vss Xgatesmall

*connect Xgates and grounding

Xconnect12_21 12_21 phup1 phup2 con12_21bar connect12_21 vdd vss NAND_AND3

Xconnect13_31 13_31 phup1 phup3 con13_31bar connect13_31 vdd vss NAND_AND3

Xconnect23_32 23_32 phup2 phup3 con23_32bar connect23_32 vdd vss NAND_AND3

XANDspkr12_21 12_21 con12_21bar spkr12_21 vdd vss AND2

XANDspkr13_31 13_31 con13_31bar spkr13_31 vdd vss AND2

XANDspkr23_32 23_32 con23_32bar spkr23_32 vdd vss AND2

Xxgate12_21_spkr  spkr12_21 spkr1 spkr2 vdd vss XGATEsmall

Xxgate13_31_spkr  spkr13_31 spkr1 spkr3 vdd vss XGATEsmall

Xxgate23_32_spkr  spkr23_32 spkr2 spkr3 vdd vss XGATEsmall

Xxgate12_21_1  connect12_21 mic1 spkr2 vdd vss XGATE

Xxgate12_21_2  connect12_21 mic2 spkr1 vdd vss XGATE

Xxgate13_31_1  connect13_31 mic1 spkr3 vdd vss XGATE

Xxgate13_31_2  connect13_31 mic3 spkr1 vdd vss XGATE

Xxgate23_32_1  connect23_32 mic2 spkr3 vdd vss XGATE

Xxgate23_32_2  connect23_32 mic3 spkr2 vdd vss XGATE

Xungnd1 phup1 ringer1 ungnd1x vdd vss NOR2

Xungnd2 phup2 ringer2 ungnd2x vdd vss NOR2

Xungnd3 phup3 ringer3 ungnd3x vdd vss NOR2

X_ORungnd1x ungnd1x dialup1 ungnd1 vdd vss OR2

X_ORungnd2x ungnd2x dialup2 ungnd2 vdd vss OR2

X_ORungnd3x ungnd3x dialup3 ungnd3 vdd vss OR2

Xxgateungnd1 ungnd1 spkr1 vss vdd vss XGATEsmall

Xxgateungnd2 ungnd2 spkr2 vss vdd vss XGATEsmall

Xxgateungnd3 ungnd3 spkr3 vss vdd vss XGATEsmall

*-----Ring toner ------------

Xringer1 spkr12_21 spkr13_31 ringer1 vdd vss OR2

Xringer2 spkr12_21 spkr23_32 ringer2 vdd vss OR2

Xringer3 spkr13_31 spkr23_32 ringer3 vdd vss OR2

Xxgatertone1  ringer1 spkr1 Rtone vdd vss XGATEsmall

Xxgatertone2  ringer2 spkr2 Rtone vdd vss XGATEsmall

Xxgatertone3  ringer3 spkr3 Rtone vdd vss XGATEsmall

*----------busytone-------------------

Xbztoner1 ANYsel1 dtoner1bar L1busyinv bztoner1 vdd vss AND3

Xbztoner2 ANYsel2 dtoner2bar L2busyinv bztoner2 vdd vss AND3

Xbztoner3 ANYsel3 dtoner3bar L3busyinv bztoner3 vdd vss AND3

Xxgatebztone1  bztoner1 spkr1 bztone vdd vss XGATEsmall

Xxgatebztone2  bztoner2 spkr2 bztone vdd vss XGATEsmall

Xxgatebztone3  bztoner3 spkr3 bztone vdd vss XGATEsmall

.IC V(vmpin)=0 V(12_21)=0 V(13_31)=0 V(23_32)=0  V(dtoner1)=0 V(dtoner2)=0  V(dtoner3)=0

** Pushbuttons

vpush13 push13 0 DC 0

vpush12 push12 0 PWL (0 0 100ns 0 100.1ns 1 109.9ns 1 110ns 0 1800ns 0)

vpush21 push21 0 DC 0

vpush23 push23 0 PWL (0 0 100ns 0 100.1ns 0 109.9ns 0 110ns 0 1800ns 0)

vpush31 push31 0 PWL (0 0 300ns 0 300.1ns 1 309.9ns 1 310ns 0 1800ns 0)

vpush32 push32 0 DC 0

* vreset simulates phone up and down

vreset1 pushreset1 0 PWL (0 0 40ns 0 40.1ns 1 619.9ns 1 620ns 0 1400ns 0)

vreset2 pushreset2 0 PWL (0 0 300ns 0 300.1ns 1 469.9ns 1 470ns 0 1400ns 0)

vreset3 pushreset3 0 PWL (0 0 240ns 0 240.1ns 1 519.9ns 1 520ns 0 1400ns 0)

vch3 mic3 0 PULSE (0 1 10ns 0.1ns 0.1ns 19.8ns 40ns)

vch2 mic2 0 PULSE (0 1 10ns 0.1ns 0.1ns 49.8ns 100ns)

vch1 mic1 0 PULSE (0 1 10ns 0.1ns 0.1ns 4.8ns 10ns)

Vdtome dtone 0 SINE(0.5 0.5 50000000 0 0 0 )

VRtone rtone 0 SINE(0.5 0.5 200000000 0 0 0 )

Vbztone bztone 0 PULSE (0.25 0.75 10ns 0.1ns 0.1ns 9.8ns 20ns)

VHI vdd 0 DC 1

VHI18 vdd18 0 DC 1.8

VLO vss 0 DC 0

.TRAN  1ns 700ns

**PTM 45nm LP model used for simulation

** Simulator used LTSpice IV

***

scilab code for X-Y data plotting and Yav estimation (Item#455)

//current vs time plotting and average current calculation

clear

clf

fd=mopen('C:\Users\Arya\Documents\IVvin.txt','r')

jj=0

trapsum=0

while (~meof(fd)) do

lineread = mgetl(fd,1)

if regexp(lineread, '/.*[0-9].*\s+.*[0-9].*/') then

ss=strsplit(lineread, "/\s+/")

jj=jj+1

x(jj)=evstr(ss(1))

y(jj)=evstr(ss(2))

if jj > 1 then

trapsum=trapsum + ((y(jj)+ y(jj-1))/2)*(x(jj) - x(jj-1))

end

end

end

yav= trapsum/(x(jj)-x(1))

clf

plot2d(x, y)

a=gca()

a.thickness=3

a.font_style=4

a.font_size=3

a.x_label.text="Time(s)"

a.x_label.font_size=3

a.x_label.font_style=4

a.y_label.text="Current, I(A)"

a.y_label.font_size=3

a.y_label.font_style=4

a.title.text="Current at Vin=Vdc"

a.title.font_size=3

a.title.font_style=4

b=get("hdl")

b.children.thickness=3

b.children.mark_mode="on"

b.children.mark_style=4

b.children.mark_foreground=5

b.children.foreground=12

lstr="Iav="+string(yav)

h1=legend([lstr])

h1.line_mode = "off"

mclose('all')

Arya Raychaudhuri

All snippets presented here are strictly proprietary to LVS DEBUG SOLUTIONS LLC, any commercial use of these is prohibited, without proper distribution agreement with the owner.